1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Panasonic Corporation
3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/iopoll.h>
14*4882a593Smuzhiyun #include <linux/sizes.h>
15*4882a593Smuzhiyun #include <linux/errno.h>
16*4882a593Smuzhiyun #include <i2c.h>
17*4882a593Smuzhiyun #include <fdtdec.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct uniphier_fi2c_regs {
20*4882a593Smuzhiyun u32 cr; /* control register */
21*4882a593Smuzhiyun #define I2C_CR_MST (1 << 3) /* master mode */
22*4882a593Smuzhiyun #define I2C_CR_STA (1 << 2) /* start condition */
23*4882a593Smuzhiyun #define I2C_CR_STO (1 << 1) /* stop condition */
24*4882a593Smuzhiyun #define I2C_CR_NACK (1 << 0) /* not ACK */
25*4882a593Smuzhiyun u32 dttx; /* send FIFO (write-only) */
26*4882a593Smuzhiyun #define dtrx dttx /* receive FIFO (read-only) */
27*4882a593Smuzhiyun #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
28*4882a593Smuzhiyun #define I2C_DTTX_RD (1 << 0) /* read */
29*4882a593Smuzhiyun u32 __reserved; /* no register at offset 0x08 */
30*4882a593Smuzhiyun u32 slad; /* slave address */
31*4882a593Smuzhiyun u32 cyc; /* clock cycle control */
32*4882a593Smuzhiyun u32 lctl; /* clock low period control */
33*4882a593Smuzhiyun u32 ssut; /* restart/stop setup time control */
34*4882a593Smuzhiyun u32 dsut; /* data setup time control */
35*4882a593Smuzhiyun u32 intr; /* interrupt status */
36*4882a593Smuzhiyun u32 ie; /* interrupt enable */
37*4882a593Smuzhiyun u32 ic; /* interrupt clear */
38*4882a593Smuzhiyun #define I2C_INT_TE (1 << 9) /* TX FIFO empty */
39*4882a593Smuzhiyun #define I2C_INT_RB (1 << 4) /* received specified bytes */
40*4882a593Smuzhiyun #define I2C_INT_NA (1 << 2) /* no answer */
41*4882a593Smuzhiyun #define I2C_INT_AL (1 << 1) /* arbitration lost */
42*4882a593Smuzhiyun u32 sr; /* status register */
43*4882a593Smuzhiyun #define I2C_SR_DB (1 << 12) /* device busy */
44*4882a593Smuzhiyun #define I2C_SR_BB (1 << 8) /* bus busy */
45*4882a593Smuzhiyun #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
46*4882a593Smuzhiyun #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
47*4882a593Smuzhiyun #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
48*4882a593Smuzhiyun #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
49*4882a593Smuzhiyun u32 __reserved2; /* no register at offset 0x30 */
50*4882a593Smuzhiyun u32 rst; /* reset control */
51*4882a593Smuzhiyun #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
52*4882a593Smuzhiyun #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
53*4882a593Smuzhiyun #define I2C_RST_RST (1 << 0) /* forcible bus reset */
54*4882a593Smuzhiyun u32 bm; /* bus monitor */
55*4882a593Smuzhiyun u32 noise; /* noise filter control */
56*4882a593Smuzhiyun u32 tbc; /* Tx byte count setting */
57*4882a593Smuzhiyun u32 rbc; /* Rx byte count setting */
58*4882a593Smuzhiyun u32 tbcm; /* Tx byte count monitor */
59*4882a593Smuzhiyun u32 rbcm; /* Rx byte count monitor */
60*4882a593Smuzhiyun u32 brst; /* bus reset */
61*4882a593Smuzhiyun #define I2C_BRST_FOEN (1 << 1) /* normal operation */
62*4882a593Smuzhiyun #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define FIOCLK 50000000
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct uniphier_fi2c_dev {
68*4882a593Smuzhiyun struct uniphier_fi2c_regs __iomem *regs; /* register base */
69*4882a593Smuzhiyun unsigned long fioclk; /* internal operation clock */
70*4882a593Smuzhiyun unsigned long timeout; /* time out (us) */
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
reset_bus(struct uniphier_fi2c_regs __iomem * regs)73*4882a593Smuzhiyun static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun u32 val;
76*4882a593Smuzhiyun int ret;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* bus forcible reset */
79*4882a593Smuzhiyun writel(I2C_RST_RST, ®s->rst);
80*4882a593Smuzhiyun ret = readl_poll_timeout(®s->rst, val, !(val & I2C_RST_RST), 1);
81*4882a593Smuzhiyun if (ret < 0)
82*4882a593Smuzhiyun debug("error: fail to reset I2C controller\n");
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
check_device_busy(struct uniphier_fi2c_regs __iomem * regs)87*4882a593Smuzhiyun static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun u32 val;
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = readl_poll_timeout(®s->sr, val, !(val & I2C_SR_DB), 100);
93*4882a593Smuzhiyun if (ret < 0) {
94*4882a593Smuzhiyun debug("error: device busy too long. reset...\n");
95*4882a593Smuzhiyun ret = reset_bus(regs);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return ret;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
uniphier_fi2c_probe(struct udevice * dev)101*4882a593Smuzhiyun static int uniphier_fi2c_probe(struct udevice *dev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun fdt_addr_t addr;
104*4882a593Smuzhiyun struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
105*4882a593Smuzhiyun int ret;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun addr = devfdt_get_addr(dev);
108*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
109*4882a593Smuzhiyun return -EINVAL;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun priv->regs = devm_ioremap(dev, addr, SZ_128);
112*4882a593Smuzhiyun if (!priv->regs)
113*4882a593Smuzhiyun return -ENOMEM;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun priv->fioclk = FIOCLK;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* bus forcible reset */
118*4882a593Smuzhiyun ret = reset_bus(priv->regs);
119*4882a593Smuzhiyun if (ret < 0)
120*4882a593Smuzhiyun return ret;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
wait_for_irq(struct uniphier_fi2c_dev * dev,u32 flags,bool * stop)127*4882a593Smuzhiyun static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
128*4882a593Smuzhiyun bool *stop)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun u32 irq;
131*4882a593Smuzhiyun int ret;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ret = readl_poll_timeout(&dev->regs->intr, irq, irq & flags,
134*4882a593Smuzhiyun dev->timeout);
135*4882a593Smuzhiyun if (ret < 0) {
136*4882a593Smuzhiyun debug("error: time out\n");
137*4882a593Smuzhiyun return ret;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (irq & I2C_INT_AL) {
141*4882a593Smuzhiyun debug("error: arbitration lost\n");
142*4882a593Smuzhiyun *stop = false;
143*4882a593Smuzhiyun return ret;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (irq & I2C_INT_NA) {
147*4882a593Smuzhiyun debug("error: no answer\n");
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
issue_stop(struct uniphier_fi2c_dev * dev,int old_ret)154*4882a593Smuzhiyun static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun int ret;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun debug("stop condition\n");
159*4882a593Smuzhiyun writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun ret = check_device_busy(dev->regs);
162*4882a593Smuzhiyun if (ret < 0)
163*4882a593Smuzhiyun debug("error: device busy after operation\n");
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return old_ret ? old_ret : ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
uniphier_fi2c_transmit(struct uniphier_fi2c_dev * dev,uint addr,uint len,const u8 * buf,bool * stop)168*4882a593Smuzhiyun static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
169*4882a593Smuzhiyun uint len, const u8 *buf, bool *stop)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun int ret;
172*4882a593Smuzhiyun const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
173*4882a593Smuzhiyun struct uniphier_fi2c_regs __iomem *regs = dev->regs;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun debug("%s: addr = %x, len = %d\n", __func__, addr, len);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun writel(I2C_DTTX_CMD | addr << 1, ®s->dttx);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun writel(irq_flags, ®s->ie);
180*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun debug("start condition\n");
183*4882a593Smuzhiyun writel(I2C_CR_MST | I2C_CR_STA, ®s->cr);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = wait_for_irq(dev, irq_flags, stop);
186*4882a593Smuzhiyun if (ret < 0)
187*4882a593Smuzhiyun goto error;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun while (len--) {
190*4882a593Smuzhiyun debug("sending %x\n", *buf);
191*4882a593Smuzhiyun writel(*buf++, ®s->dttx);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = wait_for_irq(dev, irq_flags, stop);
196*4882a593Smuzhiyun if (ret < 0)
197*4882a593Smuzhiyun goto error;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun error:
201*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (*stop)
204*4882a593Smuzhiyun ret = issue_stop(dev, ret);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return ret;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
uniphier_fi2c_receive(struct uniphier_fi2c_dev * dev,uint addr,uint len,u8 * buf,bool * stop)209*4882a593Smuzhiyun static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
210*4882a593Smuzhiyun uint len, u8 *buf, bool *stop)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun int ret = 0;
213*4882a593Smuzhiyun const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
214*4882a593Smuzhiyun struct uniphier_fi2c_regs __iomem *regs = dev->regs;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun debug("%s: addr = %x, len = %d\n", __func__, addr, len);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /*
219*4882a593Smuzhiyun * In case 'len == 0', only the slave address should be sent
220*4882a593Smuzhiyun * for probing, which is covered by the transmit function.
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun if (len == 0)
223*4882a593Smuzhiyun return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun writel(0, ®s->rbc);
228*4882a593Smuzhiyun writel(irq_flags, ®s->ie);
229*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun debug("start condition\n");
232*4882a593Smuzhiyun writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
233*4882a593Smuzhiyun ®s->cr);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun while (len--) {
236*4882a593Smuzhiyun ret = wait_for_irq(dev, irq_flags, stop);
237*4882a593Smuzhiyun if (ret < 0)
238*4882a593Smuzhiyun goto error;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun *buf++ = readl(®s->dtrx);
241*4882a593Smuzhiyun debug("received %x\n", *(buf - 1));
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (len == 1)
244*4882a593Smuzhiyun writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun error:
250*4882a593Smuzhiyun writel(irq_flags, ®s->ic);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (*stop)
253*4882a593Smuzhiyun ret = issue_stop(dev, ret);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun return ret;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
uniphier_fi2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)258*4882a593Smuzhiyun static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
259*4882a593Smuzhiyun int nmsgs)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun int ret;
262*4882a593Smuzhiyun struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
263*4882a593Smuzhiyun bool stop;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun ret = check_device_busy(dev->regs);
266*4882a593Smuzhiyun if (ret < 0)
267*4882a593Smuzhiyun return ret;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun for (; nmsgs > 0; nmsgs--, msg++) {
270*4882a593Smuzhiyun /* If next message is read, skip the stop condition */
271*4882a593Smuzhiyun stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun if (msg->flags & I2C_M_RD)
274*4882a593Smuzhiyun ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
275*4882a593Smuzhiyun msg->buf, &stop);
276*4882a593Smuzhiyun else
277*4882a593Smuzhiyun ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
278*4882a593Smuzhiyun msg->buf, &stop);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun if (ret < 0)
281*4882a593Smuzhiyun break;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return ret;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
uniphier_fi2c_set_bus_speed(struct udevice * bus,unsigned int speed)287*4882a593Smuzhiyun static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun int ret;
290*4882a593Smuzhiyun unsigned int clk_count;
291*4882a593Smuzhiyun struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
292*4882a593Smuzhiyun struct uniphier_fi2c_regs __iomem *regs = dev->regs;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* max supported frequency is 400 kHz */
295*4882a593Smuzhiyun if (speed > 400000)
296*4882a593Smuzhiyun return -EINVAL;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun ret = check_device_busy(dev->regs);
299*4882a593Smuzhiyun if (ret < 0)
300*4882a593Smuzhiyun return ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* make sure the bus is idle when changing the frequency */
303*4882a593Smuzhiyun writel(I2C_BRST_RSCLO, ®s->brst);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun clk_count = dev->fioclk / speed;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun writel(clk_count, ®s->cyc);
308*4882a593Smuzhiyun writel(clk_count / 2, ®s->lctl);
309*4882a593Smuzhiyun writel(clk_count / 2, ®s->ssut);
310*4882a593Smuzhiyun writel(clk_count / 16, ®s->dsut);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /*
315*4882a593Smuzhiyun * Theoretically, each byte can be transferred in
316*4882a593Smuzhiyun * 1000000 * 9 / speed usec.
317*4882a593Smuzhiyun * This time out value is long enough.
318*4882a593Smuzhiyun */
319*4882a593Smuzhiyun dev->timeout = 100000000L / speed;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun return 0;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun static const struct dm_i2c_ops uniphier_fi2c_ops = {
325*4882a593Smuzhiyun .xfer = uniphier_fi2c_xfer,
326*4882a593Smuzhiyun .set_bus_speed = uniphier_fi2c_set_bus_speed,
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static const struct udevice_id uniphier_fi2c_of_match[] = {
330*4882a593Smuzhiyun { .compatible = "socionext,uniphier-fi2c" },
331*4882a593Smuzhiyun { /* sentinel */ }
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun U_BOOT_DRIVER(uniphier_fi2c) = {
335*4882a593Smuzhiyun .name = "uniphier-fi2c",
336*4882a593Smuzhiyun .id = UCLASS_I2C,
337*4882a593Smuzhiyun .of_match = uniphier_fi2c_of_match,
338*4882a593Smuzhiyun .probe = uniphier_fi2c_probe,
339*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
340*4882a593Smuzhiyun .ops = &uniphier_fi2c_ops,
341*4882a593Smuzhiyun };
342