1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Faraday I2C Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2010 Faraday Technology 5*4882a593Smuzhiyun * Dante Su <dantesu@faraday-tech.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __FTI2C010_H 11*4882a593Smuzhiyun #define __FTI2C010_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * FTI2C010 registers 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun struct fti2c010_regs { 17*4882a593Smuzhiyun uint32_t cr; /* 0x00: control register */ 18*4882a593Smuzhiyun uint32_t sr; /* 0x04: status register */ 19*4882a593Smuzhiyun uint32_t cdr; /* 0x08: clock division register */ 20*4882a593Smuzhiyun uint32_t dr; /* 0x0c: data register */ 21*4882a593Smuzhiyun uint32_t sar; /* 0x10: slave address register */ 22*4882a593Smuzhiyun uint32_t tgsr;/* 0x14: time & glitch suppression register */ 23*4882a593Smuzhiyun uint32_t bmr; /* 0x18: bus monitor register */ 24*4882a593Smuzhiyun uint32_t rsvd[5]; 25*4882a593Smuzhiyun uint32_t revr;/* 0x30: revision register */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * control register 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */ 32*4882a593Smuzhiyun #define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */ 33*4882a593Smuzhiyun #define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */ 34*4882a593Smuzhiyun #define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */ 35*4882a593Smuzhiyun #define CR_DRIRQ 0x200 /* rx interrupt (both) */ 36*4882a593Smuzhiyun #define CR_DTIRQ 0x100 /* tx interrupt (both) */ 37*4882a593Smuzhiyun #define CR_TBEN 0x80 /* tx enable (both) */ 38*4882a593Smuzhiyun #define CR_NAK 0x40 /* NACK (both) */ 39*4882a593Smuzhiyun #define CR_STOP 0x20 /* stop (master) */ 40*4882a593Smuzhiyun #define CR_START 0x10 /* start (master) */ 41*4882a593Smuzhiyun #define CR_GCEN 0x8 /* general call support (slave) */ 42*4882a593Smuzhiyun #define CR_SCLEN 0x4 /* enable clock out (master) */ 43*4882a593Smuzhiyun #define CR_I2CEN 0x2 /* enable I2C (both) */ 44*4882a593Smuzhiyun #define CR_I2CRST 0x1 /* reset I2C (both) */ 45*4882a593Smuzhiyun #define CR_ENABLE \ 46*4882a593Smuzhiyun (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * status register 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define SR_CLRAL 0x400 /* clear arbitration lost */ 52*4882a593Smuzhiyun #define SR_CLRGC 0x200 /* clear general call */ 53*4882a593Smuzhiyun #define SR_CLRSAM 0x100 /* clear slave address match */ 54*4882a593Smuzhiyun #define SR_CLRSTOP 0x80 /* clear stop */ 55*4882a593Smuzhiyun #define SR_CLRNAKR 0x40 /* clear NACK respond */ 56*4882a593Smuzhiyun #define SR_DR 0x20 /* rx ready */ 57*4882a593Smuzhiyun #define SR_DT 0x10 /* tx done */ 58*4882a593Smuzhiyun #define SR_BB 0x8 /* bus busy */ 59*4882a593Smuzhiyun #define SR_BUSY 0x4 /* chip busy */ 60*4882a593Smuzhiyun #define SR_ACK 0x2 /* ACK/NACK received */ 61*4882a593Smuzhiyun #define SR_RW 0x1 /* set when master-rx or slave-tx mode */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * clock division register 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define CDR_DIV(n) ((n) & 0x3ffff) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * time & glitch suppression register 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define TGSR_GSR(n) (((n) & 0x7) << 10) 72*4882a593Smuzhiyun #define TGSR_TSR(n) ((n) & 0x3ff) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * bus monitor register 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define BMR_SCL 0x2 /* SCL is pull-up */ 78*4882a593Smuzhiyun #define BMR_SDA 0x1 /* SDA is pull-up */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* __FTI2C010_H */ 81