1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DW_I2C_H_ 9*4882a593Smuzhiyun #define __DW_I2C_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct i2c_regs { 12*4882a593Smuzhiyun u32 ic_con; /* 0x00 */ 13*4882a593Smuzhiyun u32 ic_tar; /* 0x04 */ 14*4882a593Smuzhiyun u32 ic_sar; /* 0x08 */ 15*4882a593Smuzhiyun u32 ic_hs_maddr; /* 0x0c */ 16*4882a593Smuzhiyun u32 ic_cmd_data; /* 0x10 */ 17*4882a593Smuzhiyun u32 ic_ss_scl_hcnt; /* 0x14 */ 18*4882a593Smuzhiyun u32 ic_ss_scl_lcnt; /* 0x18 */ 19*4882a593Smuzhiyun u32 ic_fs_scl_hcnt; /* 0x1c */ 20*4882a593Smuzhiyun u32 ic_fs_scl_lcnt; /* 0x20 */ 21*4882a593Smuzhiyun u32 ic_hs_scl_hcnt; /* 0x24 */ 22*4882a593Smuzhiyun u32 ic_hs_scl_lcnt; /* 0x28 */ 23*4882a593Smuzhiyun u32 ic_intr_stat; /* 0x2c */ 24*4882a593Smuzhiyun u32 ic_intr_mask; /* 0x30 */ 25*4882a593Smuzhiyun u32 ic_raw_intr_stat; /* 0x34 */ 26*4882a593Smuzhiyun u32 ic_rx_tl; /* 0x38 */ 27*4882a593Smuzhiyun u32 ic_tx_tl; /* 0x3c */ 28*4882a593Smuzhiyun u32 ic_clr_intr; /* 0x40 */ 29*4882a593Smuzhiyun u32 ic_clr_rx_under; /* 0x44 */ 30*4882a593Smuzhiyun u32 ic_clr_rx_over; /* 0x48 */ 31*4882a593Smuzhiyun u32 ic_clr_tx_over; /* 0x4c */ 32*4882a593Smuzhiyun u32 ic_clr_rd_req; /* 0x50 */ 33*4882a593Smuzhiyun u32 ic_clr_tx_abrt; /* 0x54 */ 34*4882a593Smuzhiyun u32 ic_clr_rx_done; /* 0x58 */ 35*4882a593Smuzhiyun u32 ic_clr_activity; /* 0x5c */ 36*4882a593Smuzhiyun u32 ic_clr_stop_det; /* 0x60 */ 37*4882a593Smuzhiyun u32 ic_clr_start_det; /* 0x64 */ 38*4882a593Smuzhiyun u32 ic_clr_gen_call; /* 0x68 */ 39*4882a593Smuzhiyun u32 ic_enable; /* 0x6c */ 40*4882a593Smuzhiyun u32 ic_status; /* 0x70 */ 41*4882a593Smuzhiyun u32 ic_txflr; /* 0x74 */ 42*4882a593Smuzhiyun u32 ic_rxflr; /* 0x78 */ 43*4882a593Smuzhiyun u32 ic_sda_hold; /* 0x7c */ 44*4882a593Smuzhiyun u32 ic_tx_abrt_source; /* 0x80 */ 45*4882a593Smuzhiyun u8 res1[0x18]; /* 0x84 */ 46*4882a593Smuzhiyun u32 ic_enable_status; /* 0x9c */ 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #if !defined(IC_CLK) 50*4882a593Smuzhiyun #define IC_CLK 166 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun #define NANO_TO_MICRO 1000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* High and low times in different speed modes (in ns) */ 55*4882a593Smuzhiyun #define MIN_SS_SCL_HIGHTIME 4000 56*4882a593Smuzhiyun #define MIN_SS_SCL_LOWTIME 4700 57*4882a593Smuzhiyun #define MIN_FS_SCL_HIGHTIME 600 58*4882a593Smuzhiyun #define MIN_FS_SCL_LOWTIME 1300 59*4882a593Smuzhiyun #define MIN_HS_SCL_HIGHTIME 60 60*4882a593Smuzhiyun #define MIN_HS_SCL_LOWTIME 160 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Worst case timeout for 1 byte is kept as 2ms */ 63*4882a593Smuzhiyun #define I2C_BYTE_TO (CONFIG_SYS_HZ/500) 64*4882a593Smuzhiyun #define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) 65*4882a593Smuzhiyun #define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* i2c control register definitions */ 68*4882a593Smuzhiyun #define IC_CON_SD 0x0040 69*4882a593Smuzhiyun #define IC_CON_RE 0x0020 70*4882a593Smuzhiyun #define IC_CON_10BITADDRMASTER 0x0010 71*4882a593Smuzhiyun #define IC_CON_10BITADDR_SLAVE 0x0008 72*4882a593Smuzhiyun #define IC_CON_SPD_MSK 0x0006 73*4882a593Smuzhiyun #define IC_CON_SPD_SS 0x0002 74*4882a593Smuzhiyun #define IC_CON_SPD_FS 0x0004 75*4882a593Smuzhiyun #define IC_CON_SPD_HS 0x0006 76*4882a593Smuzhiyun #define IC_CON_MM 0x0001 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* i2c target address register definitions */ 79*4882a593Smuzhiyun #define TAR_ADDR 0x0050 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* i2c slave address register definitions */ 82*4882a593Smuzhiyun #define IC_SLAVE_ADDR 0x0002 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* i2c data buffer and command register definitions */ 85*4882a593Smuzhiyun #define IC_CMD 0x0100 86*4882a593Smuzhiyun #define IC_STOP 0x0200 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* i2c interrupt status register definitions */ 89*4882a593Smuzhiyun #define IC_GEN_CALL 0x0800 90*4882a593Smuzhiyun #define IC_START_DET 0x0400 91*4882a593Smuzhiyun #define IC_STOP_DET 0x0200 92*4882a593Smuzhiyun #define IC_ACTIVITY 0x0100 93*4882a593Smuzhiyun #define IC_RX_DONE 0x0080 94*4882a593Smuzhiyun #define IC_TX_ABRT 0x0040 95*4882a593Smuzhiyun #define IC_RD_REQ 0x0020 96*4882a593Smuzhiyun #define IC_TX_EMPTY 0x0010 97*4882a593Smuzhiyun #define IC_TX_OVER 0x0008 98*4882a593Smuzhiyun #define IC_RX_FULL 0x0004 99*4882a593Smuzhiyun #define IC_RX_OVER 0x0002 100*4882a593Smuzhiyun #define IC_RX_UNDER 0x0001 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* fifo threshold register definitions */ 103*4882a593Smuzhiyun #define IC_TL0 0x00 104*4882a593Smuzhiyun #define IC_TL1 0x01 105*4882a593Smuzhiyun #define IC_TL2 0x02 106*4882a593Smuzhiyun #define IC_TL3 0x03 107*4882a593Smuzhiyun #define IC_TL4 0x04 108*4882a593Smuzhiyun #define IC_TL5 0x05 109*4882a593Smuzhiyun #define IC_TL6 0x06 110*4882a593Smuzhiyun #define IC_TL7 0x07 111*4882a593Smuzhiyun #define IC_RX_TL IC_TL0 112*4882a593Smuzhiyun #define IC_TX_TL IC_TL0 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* i2c enable register definitions */ 115*4882a593Smuzhiyun #define IC_ENABLE_0B 0x0001 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* i2c status register definitions */ 118*4882a593Smuzhiyun #define IC_STATUS_SA 0x0040 119*4882a593Smuzhiyun #define IC_STATUS_MA 0x0020 120*4882a593Smuzhiyun #define IC_STATUS_RFF 0x0010 121*4882a593Smuzhiyun #define IC_STATUS_RFNE 0x0008 122*4882a593Smuzhiyun #define IC_STATUS_TFE 0x0004 123*4882a593Smuzhiyun #define IC_STATUS_TFNF 0x0002 124*4882a593Smuzhiyun #define IC_STATUS_ACT 0x0001 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Speed Selection */ 127*4882a593Smuzhiyun #define IC_SPEED_MODE_STANDARD 1 128*4882a593Smuzhiyun #define IC_SPEED_MODE_FAST 2 129*4882a593Smuzhiyun #define IC_SPEED_MODE_MAX 3 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define I2C_MAX_SPEED 3400000 132*4882a593Smuzhiyun #define I2C_FAST_SPEED 400000 133*4882a593Smuzhiyun #define I2C_STANDARD_SPEED 100000 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif /* __DW_I2C_H_ */ 136