1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004-2014 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef _DAVINCI_I2C_H_ 10*4882a593Smuzhiyun #define _DAVINCI_I2C_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define I2C_WRITE 0 13*4882a593Smuzhiyun #define I2C_READ 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct i2c_regs { 16*4882a593Smuzhiyun u32 i2c_oa; 17*4882a593Smuzhiyun u32 i2c_ie; 18*4882a593Smuzhiyun u32 i2c_stat; 19*4882a593Smuzhiyun u32 i2c_scll; 20*4882a593Smuzhiyun u32 i2c_sclh; 21*4882a593Smuzhiyun u32 i2c_cnt; 22*4882a593Smuzhiyun u32 i2c_drr; 23*4882a593Smuzhiyun u32 i2c_sa; 24*4882a593Smuzhiyun u32 i2c_dxr; 25*4882a593Smuzhiyun u32 i2c_con; 26*4882a593Smuzhiyun u32 i2c_iv; 27*4882a593Smuzhiyun u32 res_2c; 28*4882a593Smuzhiyun u32 i2c_psc; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* I2C masks */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* I2C Interrupt Enable Register (I2C_IE): */ 34*4882a593Smuzhiyun #define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ 35*4882a593Smuzhiyun #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 36*4882a593Smuzhiyun #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 37*4882a593Smuzhiyun #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 38*4882a593Smuzhiyun #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 39*4882a593Smuzhiyun #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* I2C Status Register (I2C_STAT): */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define I2C_STAT_BB (1 << 12) /* Bus busy */ 44*4882a593Smuzhiyun #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 45*4882a593Smuzhiyun #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 46*4882a593Smuzhiyun #define I2C_STAT_AAS (1 << 9) /* Address as slave */ 47*4882a593Smuzhiyun #define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ 48*4882a593Smuzhiyun #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 49*4882a593Smuzhiyun #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 50*4882a593Smuzhiyun #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 51*4882a593Smuzhiyun #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 52*4882a593Smuzhiyun #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* I2C Interrupt Code Register (I2C_INTCODE): */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define I2C_INTCODE_MASK 7 57*4882a593Smuzhiyun #define I2C_INTCODE_NONE 0 58*4882a593Smuzhiyun #define I2C_INTCODE_AL 1 /* Arbitration lost */ 59*4882a593Smuzhiyun #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 60*4882a593Smuzhiyun #define I2C_INTCODE_ARDY 3 /* Register access ready */ 61*4882a593Smuzhiyun #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 62*4882a593Smuzhiyun #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 63*4882a593Smuzhiyun #define I2C_INTCODE_SCD 6 /* Stop condition detect */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* I2C Configuration Register (I2C_CON): */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define I2C_CON_EN (1 << 5) /* I2C module enable */ 68*4882a593Smuzhiyun #define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ 69*4882a593Smuzhiyun #define I2C_CON_MST (1 << 10) /* Master/slave mode */ 70*4882a593Smuzhiyun #define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ 71*4882a593Smuzhiyun #define I2C_CON_XA (1 << 8) /* Expand address */ 72*4882a593Smuzhiyun #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ 73*4882a593Smuzhiyun #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ 74*4882a593Smuzhiyun #define I2C_CON_FREE (1 << 14) /* Free run on emulation */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79