1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012-2020 ASPEED Technology Inc.
3*4882a593Smuzhiyun * Copyright 2016 IBM Corporation
4*4882a593Smuzhiyun * Copyright 2017 Google, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <clk.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <fdtdec.h>
14*4882a593Smuzhiyun #include <i2c.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <asm/arch/scu_ast2500.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "ast_i2c.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define I2C_TIMEOUT_US 100000
21*4882a593Smuzhiyun #define I2C_SLEEP_STEP_US 20
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define HIGHSPEED_TTIMEOUT 3
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Device private data
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun struct ast_i2c_priv {
31*4882a593Smuzhiyun /* This device's clock */
32*4882a593Smuzhiyun struct clk clk;
33*4882a593Smuzhiyun /* Device registers */
34*4882a593Smuzhiyun struct ast_i2c_regs *regs;
35*4882a593Smuzhiyun /* I2C speed in Hz */
36*4882a593Smuzhiyun int speed;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * Given desired divider ratio, return the value that needs to be set
41*4882a593Smuzhiyun * in Clock and AC Timing Control register
42*4882a593Smuzhiyun */
get_clk_reg_val(ulong divider_ratio)43*4882a593Smuzhiyun static u32 get_clk_reg_val(ulong divider_ratio)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun ulong inc = 0, div;
46*4882a593Smuzhiyun ulong scl_low, scl_high, data;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun for (div = 0; divider_ratio >= 16; div++) {
49*4882a593Smuzhiyun inc |= (divider_ratio & 1);
50*4882a593Smuzhiyun divider_ratio >>= 1;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun divider_ratio += inc;
53*4882a593Smuzhiyun scl_low = (divider_ratio >> 1) - 1;
54*4882a593Smuzhiyun scl_high = divider_ratio - scl_low - 2;
55*4882a593Smuzhiyun data = I2CD_CACTC_BASE
56*4882a593Smuzhiyun | (scl_high << I2CD_TCKHIGH_SHIFT)
57*4882a593Smuzhiyun | (scl_low << I2CD_TCKLOW_SHIFT)
58*4882a593Smuzhiyun | (div << I2CD_BASE_DIV_SHIFT);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return data;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
ast_i2c_clear_interrupts(struct udevice * dev)63*4882a593Smuzhiyun static void ast_i2c_clear_interrupts(struct udevice *dev)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun writel(~0, &priv->regs->isr);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
ast_i2c_init_bus(struct udevice * dev)70*4882a593Smuzhiyun static void ast_i2c_init_bus(struct udevice *dev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Reset device */
75*4882a593Smuzhiyun writel(0, &priv->regs->fcr);
76*4882a593Smuzhiyun /* Enable Master Mode. Assuming single-master */
77*4882a593Smuzhiyun writel(I2CD_MASTER_EN
78*4882a593Smuzhiyun | I2CD_M_SDA_LOCK_EN
79*4882a593Smuzhiyun | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
80*4882a593Smuzhiyun &priv->regs->fcr);
81*4882a593Smuzhiyun /* Enable Interrupts */
82*4882a593Smuzhiyun writel(I2CD_INTR_TX_ACK
83*4882a593Smuzhiyun | I2CD_INTR_TX_NAK
84*4882a593Smuzhiyun | I2CD_INTR_RX_DONE
85*4882a593Smuzhiyun | I2CD_INTR_BUS_RECOVER_DONE
86*4882a593Smuzhiyun | I2CD_INTR_NORMAL_STOP
87*4882a593Smuzhiyun | I2CD_INTR_ABNORMAL, &priv->regs->icr);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
ast_i2c_ofdata_to_platdata(struct udevice * dev)90*4882a593Smuzhiyun static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
93*4882a593Smuzhiyun int ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun priv->regs = devfdt_get_addr_ptr(dev);
96*4882a593Smuzhiyun if (IS_ERR(priv->regs))
97*4882a593Smuzhiyun return PTR_ERR(priv->regs);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &priv->clk);
100*4882a593Smuzhiyun if (ret < 0) {
101*4882a593Smuzhiyun debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
102*4882a593Smuzhiyun ret);
103*4882a593Smuzhiyun return ret;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
ast_i2c_probe(struct udevice * dev)109*4882a593Smuzhiyun static int ast_i2c_probe(struct udevice *dev)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct ast2500_scu *scu;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun debug("Enabling I2C%u\n", dev->seq);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * Get all I2C devices out of Reset.
117*4882a593Smuzhiyun * Only needs to be done once, but doing it for every
118*4882a593Smuzhiyun * device does not hurt.
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun scu = ast_get_scu();
121*4882a593Smuzhiyun ast_scu_unlock(scu);
122*4882a593Smuzhiyun clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
123*4882a593Smuzhiyun ast_scu_lock(scu);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun ast_i2c_init_bus(dev);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
ast_i2c_wait_isr(struct udevice * dev,u32 flag)130*4882a593Smuzhiyun static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
133*4882a593Smuzhiyun int timeout = I2C_TIMEOUT_US;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
136*4882a593Smuzhiyun udelay(I2C_SLEEP_STEP_US);
137*4882a593Smuzhiyun timeout -= I2C_SLEEP_STEP_US;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ast_i2c_clear_interrupts(dev);
141*4882a593Smuzhiyun if (timeout <= 0)
142*4882a593Smuzhiyun return -ETIMEDOUT;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
ast_i2c_send_stop(struct udevice * dev)147*4882a593Smuzhiyun static int ast_i2c_send_stop(struct udevice *dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun writel(I2CD_M_STOP_CMD, &priv->regs->csr);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
ast_i2c_wait_tx(struct udevice * dev)156*4882a593Smuzhiyun static int ast_i2c_wait_tx(struct udevice *dev)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
159*4882a593Smuzhiyun int timeout = I2C_TIMEOUT_US;
160*4882a593Smuzhiyun u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
161*4882a593Smuzhiyun u32 status = readl(&priv->regs->isr) & flag;
162*4882a593Smuzhiyun int ret = 0;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun while (!status && timeout > 0) {
165*4882a593Smuzhiyun status = readl(&priv->regs->isr) & flag;
166*4882a593Smuzhiyun udelay(I2C_SLEEP_STEP_US);
167*4882a593Smuzhiyun timeout -= I2C_SLEEP_STEP_US;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (status == I2CD_INTR_TX_NAK)
171*4882a593Smuzhiyun ret = -EREMOTEIO;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun if (timeout <= 0)
174*4882a593Smuzhiyun ret = -ETIMEDOUT;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun ast_i2c_clear_interrupts(dev);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return ret;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
ast_i2c_start_txn(struct udevice * dev,uint devaddr)181*4882a593Smuzhiyun static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Start and Send Device Address */
186*4882a593Smuzhiyun writel(devaddr, &priv->regs->trbbr);
187*4882a593Smuzhiyun writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return ast_i2c_wait_tx(dev);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
ast_i2c_read_data(struct udevice * dev,u8 chip_addr,u8 * buffer,size_t len,bool send_stop)192*4882a593Smuzhiyun static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
193*4882a593Smuzhiyun size_t len, bool send_stop)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
196*4882a593Smuzhiyun u32 i2c_cmd = I2CD_M_RX_CMD;
197*4882a593Smuzhiyun int ret;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
200*4882a593Smuzhiyun if (ret < 0)
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun for (; len > 0; len--, buffer++) {
204*4882a593Smuzhiyun if (len == 1)
205*4882a593Smuzhiyun i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
206*4882a593Smuzhiyun writel(i2c_cmd, &priv->regs->csr);
207*4882a593Smuzhiyun ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
208*4882a593Smuzhiyun if (ret < 0)
209*4882a593Smuzhiyun return ret;
210*4882a593Smuzhiyun *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
211*4882a593Smuzhiyun >> I2CD_RX_DATA_SHIFT;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun ast_i2c_clear_interrupts(dev);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (send_stop)
216*4882a593Smuzhiyun return ast_i2c_send_stop(dev);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
ast_i2c_write_data(struct udevice * dev,u8 chip_addr,u8 * buffer,size_t len,bool send_stop)221*4882a593Smuzhiyun static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
222*4882a593Smuzhiyun *buffer, size_t len, bool send_stop)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
225*4882a593Smuzhiyun int ret;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = ast_i2c_start_txn(dev, (chip_addr << 1));
228*4882a593Smuzhiyun if (ret < 0)
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun for (; len > 0; len--, buffer++) {
232*4882a593Smuzhiyun writel(*buffer, &priv->regs->trbbr);
233*4882a593Smuzhiyun writel(I2CD_M_TX_CMD, &priv->regs->csr);
234*4882a593Smuzhiyun ret = ast_i2c_wait_tx(dev);
235*4882a593Smuzhiyun if (ret < 0)
236*4882a593Smuzhiyun return ret;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun if (send_stop)
240*4882a593Smuzhiyun return ast_i2c_send_stop(dev);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun return 0;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
ast_i2c_deblock(struct udevice * dev)245*4882a593Smuzhiyun static int ast_i2c_deblock(struct udevice *dev)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
248*4882a593Smuzhiyun struct ast_i2c_regs *regs = priv->regs;
249*4882a593Smuzhiyun u32 csr = readl(®s->csr);
250*4882a593Smuzhiyun bool sda_high = csr & I2CD_SDA_LINE_STS;
251*4882a593Smuzhiyun bool scl_high = csr & I2CD_SCL_LINE_STS;
252*4882a593Smuzhiyun int ret = 0;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun if (sda_high && scl_high) {
255*4882a593Smuzhiyun /* Bus is idle, no deblocking needed. */
256*4882a593Smuzhiyun return 0;
257*4882a593Smuzhiyun } else if (sda_high) {
258*4882a593Smuzhiyun /* Send stop command */
259*4882a593Smuzhiyun debug("Unterminated TXN in (%x), sending stop\n", csr);
260*4882a593Smuzhiyun ret = ast_i2c_send_stop(dev);
261*4882a593Smuzhiyun } else if (scl_high) {
262*4882a593Smuzhiyun /* Possibly stuck slave */
263*4882a593Smuzhiyun debug("Bus stuck (%x), attempting recovery\n", csr);
264*4882a593Smuzhiyun writel(I2CD_BUS_RECOVER_CMD, ®s->csr);
265*4882a593Smuzhiyun ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
266*4882a593Smuzhiyun } else {
267*4882a593Smuzhiyun /* Just try to reinit the device. */
268*4882a593Smuzhiyun ast_i2c_init_bus(dev);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
ast_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)274*4882a593Smuzhiyun static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun int ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = ast_i2c_deblock(dev);
279*4882a593Smuzhiyun if (ret < 0)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun debug("i2c_xfer: %d messages\n", nmsgs);
283*4882a593Smuzhiyun for (; nmsgs > 0; nmsgs--, msg++) {
284*4882a593Smuzhiyun if (msg->flags & I2C_M_RD) {
285*4882a593Smuzhiyun debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
286*4882a593Smuzhiyun msg->addr, msg->len, msg->flags);
287*4882a593Smuzhiyun ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
288*4882a593Smuzhiyun msg->len, (nmsgs == 1));
289*4882a593Smuzhiyun } else {
290*4882a593Smuzhiyun debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
291*4882a593Smuzhiyun msg->addr, msg->len, msg->flags);
292*4882a593Smuzhiyun ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
293*4882a593Smuzhiyun msg->len, (nmsgs == 1));
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun if (ret) {
296*4882a593Smuzhiyun debug("%s: error (%d)\n", __func__, ret);
297*4882a593Smuzhiyun return -EREMOTEIO;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun return 0;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
ast_i2c_set_speed(struct udevice * dev,unsigned int speed)304*4882a593Smuzhiyun static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun struct ast_i2c_priv *priv = dev_get_priv(dev);
307*4882a593Smuzhiyun struct ast_i2c_regs *regs = priv->regs;
308*4882a593Smuzhiyun ulong i2c_rate, divider;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
311*4882a593Smuzhiyun if (!speed) {
312*4882a593Smuzhiyun debug("No valid speed specified\n");
313*4882a593Smuzhiyun return -EINVAL;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun i2c_rate = clk_get_rate(&priv->clk);
317*4882a593Smuzhiyun divider = i2c_rate / speed;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun priv->speed = speed;
320*4882a593Smuzhiyun if (speed > I2C_HIGHSPEED_RATE) {
321*4882a593Smuzhiyun debug("Enable High Speed\n");
322*4882a593Smuzhiyun setbits_le32(®s->fcr, I2CD_M_HIGH_SPEED_EN
323*4882a593Smuzhiyun | I2CD_M_SDA_DRIVE_1T_EN
324*4882a593Smuzhiyun | I2CD_SDA_DRIVE_1T_EN);
325*4882a593Smuzhiyun writel(HIGHSPEED_TTIMEOUT, ®s->cactcr2);
326*4882a593Smuzhiyun } else {
327*4882a593Smuzhiyun debug("Enabling Normal Speed\n");
328*4882a593Smuzhiyun writel(I2CD_NO_TIMEOUT_CTRL, ®s->cactcr2);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun writel(get_clk_reg_val(divider), ®s->cactcr1);
332*4882a593Smuzhiyun ast_i2c_clear_interrupts(dev);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return 0;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun static const struct dm_i2c_ops ast_i2c_ops = {
338*4882a593Smuzhiyun .xfer = ast_i2c_xfer,
339*4882a593Smuzhiyun .set_bus_speed = ast_i2c_set_speed,
340*4882a593Smuzhiyun .deblock = ast_i2c_deblock,
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun static const struct udevice_id ast_i2c_ids[] = {
344*4882a593Smuzhiyun { .compatible = "aspeed,ast2400-i2c-bus" },
345*4882a593Smuzhiyun { .compatible = "aspeed,ast2500-i2c-bus" },
346*4882a593Smuzhiyun { },
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun U_BOOT_DRIVER(ast_i2c) = {
350*4882a593Smuzhiyun .name = "ast_i2c",
351*4882a593Smuzhiyun .id = UCLASS_I2C,
352*4882a593Smuzhiyun .of_match = ast_i2c_ids,
353*4882a593Smuzhiyun .probe = ast_i2c_probe,
354*4882a593Smuzhiyun .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
355*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
356*4882a593Smuzhiyun .ops = &ast_i2c_ops,
357*4882a593Smuzhiyun };
358