1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _TEGRA186_GPIO_PRIV_H_ 8*4882a593Smuzhiyun #define _TEGRA186_GPIO_PRIV_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * For each GPIO, there are a set of registers than affect it, all packed 12*4882a593Smuzhiyun * back-to-back. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 15*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 16*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 17*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2 18*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3 19*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0 20*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1 21*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2 22*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3 23*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4) 24*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5) 25*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6) 26*4882a593Smuzhiyun #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define TEGRA186_GPIO_INPUT 0x08 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 33*4882a593Smuzhiyun #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 36*4882a593Smuzhiyun #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * 8 GPIOs are packed into a port. Their registers appear back-to-back in the 42*4882a593Smuzhiyun * port's address space. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20 45*4882a593Smuzhiyun #define TEGRA186_GPIO_PER_GPIO_COUNT 8 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Per-port registers are packed immediately following all of a port's 49*4882a593Smuzhiyun * per-GPIO registers. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100 52*4882a593Smuzhiyun #define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4 53*4882a593Smuzhiyun #define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * The registers for multiple ports are packed together back-to-back to form 57*4882a593Smuzhiyun * the overall controller. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define TEGRA186_GPIO_PER_PORT_STRIDE 0x200 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62