xref: /OK3568_Linux_fs/u-boot/drivers/gpio/pcf8575_gpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * PCF8575 I2C GPIO EXPANDER DRIVER
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Vignesh R <vigneshr@ti.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
12*4882a593Smuzhiyun  * gpio-pcf857x Linux Kernel(v4.7) driver.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * Copyright (C) 2007 David Brownell
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun  * NOTE: The driver and devicetree bindings are borrowed from Linux
20*4882a593Smuzhiyun  * Kernel, but driver does not support all PCF857x devices. It currently
21*4882a593Smuzhiyun  * supports PCF8575 16-bit expander by TI and NXP.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * TODO(vigneshr@ti.com):
24*4882a593Smuzhiyun  * Support 8 bit PCF857x compatible expanders.
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <common.h>
28*4882a593Smuzhiyun #include <dm.h>
29*4882a593Smuzhiyun #include <i2c.h>
30*4882a593Smuzhiyun #include <asm-generic/gpio.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun struct pcf8575_chip {
35*4882a593Smuzhiyun 	int gpio_count;		/* No. GPIOs supported by the chip */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* NOTE:  these chips have strange "quasi-bidirectional" I/O pins.
38*4882a593Smuzhiyun 	 * We can't actually know whether a pin is configured (a) as output
39*4882a593Smuzhiyun 	 * and driving the signal low, or (b) as input and reporting a low
40*4882a593Smuzhiyun 	 * value ... without knowing the last value written since the chip
41*4882a593Smuzhiyun 	 * came out of reset (if any).  We can't read the latched output.
42*4882a593Smuzhiyun 	 * In short, the only reliable solution for setting up pin direction
43*4882a593Smuzhiyun 	 * is to do it explicitly.
44*4882a593Smuzhiyun 	 *
45*4882a593Smuzhiyun 	 * Using "out" avoids that trouble.  When left initialized to zero,
46*4882a593Smuzhiyun 	 * our software copy of the "latch" then matches the chip's all-ones
47*4882a593Smuzhiyun 	 * reset state.  Otherwise it flags pins to be driven low.
48*4882a593Smuzhiyun 	 */
49*4882a593Smuzhiyun 	unsigned int out;	/* software latch */
50*4882a593Smuzhiyun 	const char *bank_name;	/* Name of the expander bank */
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* Read/Write to 16-bit I/O expander */
54*4882a593Smuzhiyun 
pcf8575_i2c_write_le16(struct udevice * dev,unsigned int word)55*4882a593Smuzhiyun static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
58*4882a593Smuzhiyun 	u8 buf[2] = { word & 0xff, word >> 8, };
59*4882a593Smuzhiyun 	int ret;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	ret = dm_i2c_write(dev, 0, buf, 2);
62*4882a593Smuzhiyun 	if (ret)
63*4882a593Smuzhiyun 		printf("%s i2c write failed to addr %x\n", __func__,
64*4882a593Smuzhiyun 		       chip->chip_addr);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	return ret;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
pcf8575_i2c_read_le16(struct udevice * dev)69*4882a593Smuzhiyun static int pcf8575_i2c_read_le16(struct udevice *dev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
72*4882a593Smuzhiyun 	u8 buf[2];
73*4882a593Smuzhiyun 	int ret;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	ret = dm_i2c_read(dev, 0, buf, 2);
76*4882a593Smuzhiyun 	if (ret) {
77*4882a593Smuzhiyun 		printf("%s i2c read failed from addr %x\n", __func__,
78*4882a593Smuzhiyun 		       chip->chip_addr);
79*4882a593Smuzhiyun 		return ret;
80*4882a593Smuzhiyun 	}
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	return (buf[1] << 8) | buf[0];
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
pcf8575_direction_input(struct udevice * dev,unsigned offset)85*4882a593Smuzhiyun static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct pcf8575_chip *plat = dev_get_platdata(dev);
88*4882a593Smuzhiyun 	int status;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	plat->out |= BIT(offset);
91*4882a593Smuzhiyun 	status = pcf8575_i2c_write_le16(dev, plat->out);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	return status;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
pcf8575_direction_output(struct udevice * dev,unsigned int offset,int value)96*4882a593Smuzhiyun static int pcf8575_direction_output(struct udevice *dev,
97*4882a593Smuzhiyun 				    unsigned int offset, int value)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct pcf8575_chip *plat = dev_get_platdata(dev);
100*4882a593Smuzhiyun 	int ret;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	if (value)
103*4882a593Smuzhiyun 		plat->out |= BIT(offset);
104*4882a593Smuzhiyun 	else
105*4882a593Smuzhiyun 		plat->out &= ~BIT(offset);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	ret = pcf8575_i2c_write_le16(dev, plat->out);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return ret;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
pcf8575_get_value(struct udevice * dev,unsigned int offset)112*4882a593Smuzhiyun static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	int             value;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	value = pcf8575_i2c_read_le16(dev);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	return (value < 0) ? value : ((value & BIT(offset)) >> offset);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
pcf8575_set_value(struct udevice * dev,unsigned int offset,int value)121*4882a593Smuzhiyun static int pcf8575_set_value(struct udevice *dev, unsigned int offset,
122*4882a593Smuzhiyun 			     int value)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	return pcf8575_direction_output(dev, offset, value);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
pcf8575_ofdata_platdata(struct udevice * dev)127*4882a593Smuzhiyun static int pcf8575_ofdata_platdata(struct udevice *dev)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	struct pcf8575_chip *plat = dev_get_platdata(dev);
130*4882a593Smuzhiyun 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	int n_latch;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
135*4882a593Smuzhiyun 					     "gpio-count", 16);
136*4882a593Smuzhiyun 	uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
137*4882a593Smuzhiyun 					 "gpio-bank-name", NULL);
138*4882a593Smuzhiyun 	if (!uc_priv->bank_name)
139*4882a593Smuzhiyun 		uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
140*4882a593Smuzhiyun 						  dev_of_offset(dev), NULL);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
143*4882a593Smuzhiyun 				  "lines-initial-states", 0);
144*4882a593Smuzhiyun 	plat->out = ~n_latch;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
pcf8575_gpio_probe(struct udevice * dev)149*4882a593Smuzhiyun static int pcf8575_gpio_probe(struct udevice  *dev)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	debug("%s GPIO controller with %d gpios probed\n",
154*4882a593Smuzhiyun 	      uc_priv->bank_name, uc_priv->gpio_count);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const struct dm_gpio_ops pcf8575_gpio_ops = {
160*4882a593Smuzhiyun 	.direction_input	= pcf8575_direction_input,
161*4882a593Smuzhiyun 	.direction_output	= pcf8575_direction_output,
162*4882a593Smuzhiyun 	.get_value		= pcf8575_get_value,
163*4882a593Smuzhiyun 	.set_value		= pcf8575_set_value,
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun static const struct udevice_id pcf8575_gpio_ids[] = {
167*4882a593Smuzhiyun 	{ .compatible = "nxp,pcf8575" },
168*4882a593Smuzhiyun 	{ .compatible = "ti,pcf8575" },
169*4882a593Smuzhiyun 	{ }
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun U_BOOT_DRIVER(gpio_pcf8575) = {
173*4882a593Smuzhiyun 	.name	= "gpio_pcf8575",
174*4882a593Smuzhiyun 	.id	= UCLASS_GPIO,
175*4882a593Smuzhiyun 	.ops	= &pcf8575_gpio_ops,
176*4882a593Smuzhiyun 	.of_match = pcf8575_gpio_ids,
177*4882a593Smuzhiyun 	.ofdata_to_platdata = pcf8575_ofdata_platdata,
178*4882a593Smuzhiyun 	.probe	= pcf8575_gpio_probe,
179*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct pcf8575_chip),
180*4882a593Smuzhiyun };
181