xref: /OK3568_Linux_fs/u-boot/drivers/gpio/pca953x_gpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun  * Note:
12*4882a593Smuzhiyun  * The driver's compatible table is borrowed from Linux Kernel,
13*4882a593Smuzhiyun  * but now max supported gpio pins is 24 and only PCA953X_TYPE
14*4882a593Smuzhiyun  * is supported. PCA957X_TYPE is not supported now.
15*4882a593Smuzhiyun  * Also the Polarity Inversion feature is not supported now.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * TODO:
18*4882a593Smuzhiyun  * 1. Support PCA957X_TYPE
19*4882a593Smuzhiyun  * 2. Support 24 gpio pins
20*4882a593Smuzhiyun  * 3. Support Polarity Inversion
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <common.h>
24*4882a593Smuzhiyun #include <errno.h>
25*4882a593Smuzhiyun #include <dm.h>
26*4882a593Smuzhiyun #include <fdtdec.h>
27*4882a593Smuzhiyun #include <i2c.h>
28*4882a593Smuzhiyun #include <malloc.h>
29*4882a593Smuzhiyun #include <asm/gpio.h>
30*4882a593Smuzhiyun #include <asm/io.h>
31*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define PCA953X_INPUT           0
34*4882a593Smuzhiyun #define PCA953X_OUTPUT          1
35*4882a593Smuzhiyun #define PCA953X_INVERT          2
36*4882a593Smuzhiyun #define PCA953X_DIRECTION       3
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define PCA_GPIO_MASK           0x00FF
39*4882a593Smuzhiyun #define PCA_INT                 0x0100
40*4882a593Smuzhiyun #define PCA953X_TYPE            0x1000
41*4882a593Smuzhiyun #define PCA957X_TYPE            0x2000
42*4882a593Smuzhiyun #define PCA_TYPE_MASK           0xF000
43*4882a593Smuzhiyun #define PCA_CHIP_TYPE(x)        ((x) & PCA_TYPE_MASK)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun enum {
46*4882a593Smuzhiyun 	PCA953X_DIRECTION_IN,
47*4882a593Smuzhiyun 	PCA953X_DIRECTION_OUT,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define MAX_BANK 5
51*4882a593Smuzhiyun #define BANK_SZ 8
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun  * struct pca953x_info - Data for pca953x
57*4882a593Smuzhiyun  *
58*4882a593Smuzhiyun  * @dev: udevice structure for the device
59*4882a593Smuzhiyun  * @addr: i2c slave address
60*4882a593Smuzhiyun  * @invert: Polarity inversion or not
61*4882a593Smuzhiyun  * @gpio_count: the number of gpio pins that the device supports
62*4882a593Smuzhiyun  * @chip_type: indicate the chip type,PCA953X or PCA957X
63*4882a593Smuzhiyun  * @bank_count: the number of banks that the device supports
64*4882a593Smuzhiyun  * @reg_output: array to hold the value of output registers
65*4882a593Smuzhiyun  * @reg_direction: array to hold the value of direction registers
66*4882a593Smuzhiyun  */
67*4882a593Smuzhiyun struct pca953x_info {
68*4882a593Smuzhiyun 	struct udevice *dev;
69*4882a593Smuzhiyun 	int addr;
70*4882a593Smuzhiyun 	int invert;
71*4882a593Smuzhiyun 	int gpio_count;
72*4882a593Smuzhiyun 	int chip_type;
73*4882a593Smuzhiyun 	int bank_count;
74*4882a593Smuzhiyun 	u8 reg_output[MAX_BANK];
75*4882a593Smuzhiyun 	u8 reg_direction[MAX_BANK];
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
pca953x_write_single(struct udevice * dev,int reg,u8 val,int offset)78*4882a593Smuzhiyun static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
79*4882a593Smuzhiyun 				int offset)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
82*4882a593Smuzhiyun 	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
83*4882a593Smuzhiyun 	int off = offset / BANK_SZ;
84*4882a593Smuzhiyun 	int ret = 0;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
87*4882a593Smuzhiyun 	if (ret) {
88*4882a593Smuzhiyun 		dev_err(dev, "%s error\n", __func__);
89*4882a593Smuzhiyun 		return ret;
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
pca953x_read_single(struct udevice * dev,int reg,u8 * val,int offset)95*4882a593Smuzhiyun static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
96*4882a593Smuzhiyun 			       int offset)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
99*4882a593Smuzhiyun 	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
100*4882a593Smuzhiyun 	int off = offset / BANK_SZ;
101*4882a593Smuzhiyun 	int ret;
102*4882a593Smuzhiyun 	u8 byte;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
105*4882a593Smuzhiyun 	if (ret) {
106*4882a593Smuzhiyun 		dev_err(dev, "%s error\n", __func__);
107*4882a593Smuzhiyun 		return ret;
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	*val = byte;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
pca953x_read_regs(struct udevice * dev,int reg,u8 * val)115*4882a593Smuzhiyun static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
118*4882a593Smuzhiyun 	int ret = 0;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (info->gpio_count <= 8) {
121*4882a593Smuzhiyun 		ret = dm_i2c_read(dev, reg, val, 1);
122*4882a593Smuzhiyun 	} else if (info->gpio_count <= 16) {
123*4882a593Smuzhiyun 		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
124*4882a593Smuzhiyun 	} else if (info->gpio_count == 40) {
125*4882a593Smuzhiyun 		/* Auto increment */
126*4882a593Smuzhiyun 		ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
127*4882a593Smuzhiyun 	} else {
128*4882a593Smuzhiyun 		dev_err(dev, "Unsupported now\n");
129*4882a593Smuzhiyun 		return -EINVAL;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return ret;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
pca953x_is_output(struct udevice * dev,int offset)135*4882a593Smuzhiyun static int pca953x_is_output(struct udevice *dev, int offset)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	int bank = offset / BANK_SZ;
140*4882a593Smuzhiyun 	int off = offset % BANK_SZ;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/*0: output; 1: input */
143*4882a593Smuzhiyun 	return !(info->reg_direction[bank] & (1 << off));
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
pca953x_get_value(struct udevice * dev,unsigned offset)146*4882a593Smuzhiyun static int pca953x_get_value(struct udevice *dev, unsigned offset)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	int ret;
149*4882a593Smuzhiyun 	u8 val = 0;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	int off = offset % BANK_SZ;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
154*4882a593Smuzhiyun 	if (ret)
155*4882a593Smuzhiyun 		return ret;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	return (val >> off) & 0x1;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
pca953x_set_value(struct udevice * dev,unsigned offset,int value)160*4882a593Smuzhiyun static int pca953x_set_value(struct udevice *dev, unsigned offset,
161*4882a593Smuzhiyun 			     int value)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
164*4882a593Smuzhiyun 	int bank = offset / BANK_SZ;
165*4882a593Smuzhiyun 	int off = offset % BANK_SZ;
166*4882a593Smuzhiyun 	u8 val;
167*4882a593Smuzhiyun 	int ret;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (value)
170*4882a593Smuzhiyun 		val = info->reg_output[bank] | (1 << off);
171*4882a593Smuzhiyun 	else
172*4882a593Smuzhiyun 		val = info->reg_output[bank] & ~(1 << off);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
175*4882a593Smuzhiyun 	if (ret)
176*4882a593Smuzhiyun 		return ret;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	info->reg_output[bank] = val;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
pca953x_set_direction(struct udevice * dev,unsigned offset,int dir)183*4882a593Smuzhiyun static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
186*4882a593Smuzhiyun 	int bank = offset / BANK_SZ;
187*4882a593Smuzhiyun 	int off = offset % BANK_SZ;
188*4882a593Smuzhiyun 	u8 val;
189*4882a593Smuzhiyun 	int ret;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (dir == PCA953X_DIRECTION_IN)
192*4882a593Smuzhiyun 		val = info->reg_direction[bank] | (1 << off);
193*4882a593Smuzhiyun 	else
194*4882a593Smuzhiyun 		val = info->reg_direction[bank] & ~(1 << off);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
197*4882a593Smuzhiyun 	if (ret)
198*4882a593Smuzhiyun 		return ret;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	info->reg_direction[bank] = val;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
pca953x_direction_input(struct udevice * dev,unsigned offset)205*4882a593Smuzhiyun static int pca953x_direction_input(struct udevice *dev, unsigned offset)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
pca953x_direction_output(struct udevice * dev,unsigned offset,int value)210*4882a593Smuzhiyun static int pca953x_direction_output(struct udevice *dev, unsigned offset,
211*4882a593Smuzhiyun 				    int value)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	/* Configure output value. */
214*4882a593Smuzhiyun 	pca953x_set_value(dev, offset, value);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* Configure direction as output. */
217*4882a593Smuzhiyun 	pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	return 0;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun 
pca953x_get_function(struct udevice * dev,unsigned offset)222*4882a593Smuzhiyun static int pca953x_get_function(struct udevice *dev, unsigned offset)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	if (pca953x_is_output(dev, offset))
225*4882a593Smuzhiyun 		return GPIOF_OUTPUT;
226*4882a593Smuzhiyun 	else
227*4882a593Smuzhiyun 		return GPIOF_INPUT;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun 
pca953x_xlate(struct udevice * dev,struct gpio_desc * desc,struct ofnode_phandle_args * args)230*4882a593Smuzhiyun static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
231*4882a593Smuzhiyun 			 struct ofnode_phandle_args *args)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	desc->offset = args->args[0];
234*4882a593Smuzhiyun 	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	return 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static const struct dm_gpio_ops pca953x_ops = {
240*4882a593Smuzhiyun 	.direction_input	= pca953x_direction_input,
241*4882a593Smuzhiyun 	.direction_output	= pca953x_direction_output,
242*4882a593Smuzhiyun 	.get_value		= pca953x_get_value,
243*4882a593Smuzhiyun 	.set_value		= pca953x_set_value,
244*4882a593Smuzhiyun 	.get_function		= pca953x_get_function,
245*4882a593Smuzhiyun 	.xlate			= pca953x_xlate,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
pca953x_probe(struct udevice * dev)248*4882a593Smuzhiyun static int pca953x_probe(struct udevice *dev)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	struct pca953x_info *info = dev_get_platdata(dev);
251*4882a593Smuzhiyun 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
252*4882a593Smuzhiyun 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
253*4882a593Smuzhiyun 	char name[32], *str;
254*4882a593Smuzhiyun 	int addr;
255*4882a593Smuzhiyun 	ulong driver_data;
256*4882a593Smuzhiyun 	int ret;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	if (!info) {
259*4882a593Smuzhiyun 		dev_err(dev, "platdata not ready\n");
260*4882a593Smuzhiyun 		return -ENOMEM;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (!chip) {
264*4882a593Smuzhiyun 		dev_err(dev, "i2c not ready\n");
265*4882a593Smuzhiyun 		return -ENODEV;
266*4882a593Smuzhiyun 	}
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
269*4882a593Smuzhiyun 	if (addr == 0)
270*4882a593Smuzhiyun 		return -ENODEV;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	info->addr = addr;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	driver_data = dev_get_driver_data(dev);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	info->gpio_count = driver_data & PCA_GPIO_MASK;
277*4882a593Smuzhiyun 	if (info->gpio_count > MAX_BANK * BANK_SZ) {
278*4882a593Smuzhiyun 		dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
279*4882a593Smuzhiyun 		return -EINVAL;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	info->chip_type = PCA_CHIP_TYPE(driver_data);
283*4882a593Smuzhiyun 	if (info->chip_type != PCA953X_TYPE) {
284*4882a593Smuzhiyun 		dev_err(dev, "Only support PCA953X chip type now.\n");
285*4882a593Smuzhiyun 		return -EINVAL;
286*4882a593Smuzhiyun 	}
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
291*4882a593Smuzhiyun 	if (ret) {
292*4882a593Smuzhiyun 		dev_err(dev, "Error reading output register\n");
293*4882a593Smuzhiyun 		return ret;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
297*4882a593Smuzhiyun 	if (ret) {
298*4882a593Smuzhiyun 		dev_err(dev, "Error reading direction register\n");
299*4882a593Smuzhiyun 		return ret;
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	snprintf(name, sizeof(name), "gpio@%x_", info->addr);
303*4882a593Smuzhiyun 	str = strdup(name);
304*4882a593Smuzhiyun 	if (!str)
305*4882a593Smuzhiyun 		return -ENOMEM;
306*4882a593Smuzhiyun 	uc_priv->bank_name = str;
307*4882a593Smuzhiyun 	uc_priv->gpio_count = info->gpio_count;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	dev_dbg(dev, "%s is ready\n", str);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	return 0;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
315*4882a593Smuzhiyun #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun static const struct udevice_id pca953x_ids[] = {
318*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
319*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
320*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
321*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
322*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
323*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
324*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
325*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
326*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
327*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
328*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
329*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
330*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
331*4882a593Smuzhiyun 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
334*4882a593Smuzhiyun 	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
335*4882a593Smuzhiyun 	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
336*4882a593Smuzhiyun 	{ .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	{ .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
339*4882a593Smuzhiyun 	{ .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
340*4882a593Smuzhiyun 	{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
341*4882a593Smuzhiyun 	{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	{ .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
346*4882a593Smuzhiyun 	{ }
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun U_BOOT_DRIVER(pca953x) = {
350*4882a593Smuzhiyun 	.name		= "pca953x",
351*4882a593Smuzhiyun 	.id		= UCLASS_GPIO,
352*4882a593Smuzhiyun 	.ops		= &pca953x_ops,
353*4882a593Smuzhiyun 	.probe		= pca953x_probe,
354*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct pca953x_info),
355*4882a593Smuzhiyun 	.of_match	= pca953x_ids,
356*4882a593Smuzhiyun };
357