1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2009
3*4882a593Smuzhiyun * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011
6*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <dm.h>
13*4882a593Smuzhiyun #include <malloc.h>
14*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
15*4882a593Smuzhiyun #include <asm/gpio.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun enum mxc_gpio_direction {
19*4882a593Smuzhiyun MXC_GPIO_DIRECTION_IN,
20*4882a593Smuzhiyun MXC_GPIO_DIRECTION_OUT,
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define GPIO_PER_BANK 32
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct mxc_gpio_plat {
26*4882a593Smuzhiyun int bank_index;
27*4882a593Smuzhiyun struct gpio_regs *regs;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct mxc_bank_info {
31*4882a593Smuzhiyun struct gpio_regs *regs;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifndef CONFIG_DM_GPIO
35*4882a593Smuzhiyun #define GPIO_TO_PORT(n) (n / 32)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* GPIO port description */
38*4882a593Smuzhiyun static unsigned long gpio_ports[] = {
39*4882a593Smuzhiyun [0] = GPIO1_BASE_ADDR,
40*4882a593Smuzhiyun [1] = GPIO2_BASE_ADDR,
41*4882a593Smuzhiyun [2] = GPIO3_BASE_ADDR,
42*4882a593Smuzhiyun #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
43*4882a593Smuzhiyun defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
44*4882a593Smuzhiyun defined(CONFIG_MX7)
45*4882a593Smuzhiyun [3] = GPIO4_BASE_ADDR,
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
48*4882a593Smuzhiyun defined(CONFIG_MX7)
49*4882a593Smuzhiyun [4] = GPIO5_BASE_ADDR,
50*4882a593Smuzhiyun #ifndef CONFIG_MX6UL
51*4882a593Smuzhiyun [5] = GPIO6_BASE_ADDR,
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
55*4882a593Smuzhiyun #ifndef CONFIG_MX6UL
56*4882a593Smuzhiyun [6] = GPIO7_BASE_ADDR,
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
mxc_gpio_direction(unsigned int gpio,enum mxc_gpio_direction direction)61*4882a593Smuzhiyun static int mxc_gpio_direction(unsigned int gpio,
62*4882a593Smuzhiyun enum mxc_gpio_direction direction)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun unsigned int port = GPIO_TO_PORT(gpio);
65*4882a593Smuzhiyun struct gpio_regs *regs;
66*4882a593Smuzhiyun u32 l;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (port >= ARRAY_SIZE(gpio_ports))
69*4882a593Smuzhiyun return -1;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun gpio &= 0x1f;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun regs = (struct gpio_regs *)gpio_ports[port];
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun l = readl(®s->gpio_dir);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun switch (direction) {
78*4882a593Smuzhiyun case MXC_GPIO_DIRECTION_OUT:
79*4882a593Smuzhiyun l |= 1 << gpio;
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun case MXC_GPIO_DIRECTION_IN:
82*4882a593Smuzhiyun l &= ~(1 << gpio);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun writel(l, ®s->gpio_dir);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
gpio_set_value(unsigned gpio,int value)89*4882a593Smuzhiyun int gpio_set_value(unsigned gpio, int value)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun unsigned int port = GPIO_TO_PORT(gpio);
92*4882a593Smuzhiyun struct gpio_regs *regs;
93*4882a593Smuzhiyun u32 l;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (port >= ARRAY_SIZE(gpio_ports))
96*4882a593Smuzhiyun return -1;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun gpio &= 0x1f;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun regs = (struct gpio_regs *)gpio_ports[port];
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun l = readl(®s->gpio_dr);
103*4882a593Smuzhiyun if (value)
104*4882a593Smuzhiyun l |= 1 << gpio;
105*4882a593Smuzhiyun else
106*4882a593Smuzhiyun l &= ~(1 << gpio);
107*4882a593Smuzhiyun writel(l, ®s->gpio_dr);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
gpio_get_value(unsigned gpio)112*4882a593Smuzhiyun int gpio_get_value(unsigned gpio)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun unsigned int port = GPIO_TO_PORT(gpio);
115*4882a593Smuzhiyun struct gpio_regs *regs;
116*4882a593Smuzhiyun u32 val;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (port >= ARRAY_SIZE(gpio_ports))
119*4882a593Smuzhiyun return -1;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun gpio &= 0x1f;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun regs = (struct gpio_regs *)gpio_ports[port];
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun val = (readl(®s->gpio_psr) >> gpio) & 0x01;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return val;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
gpio_request(unsigned gpio,const char * label)130*4882a593Smuzhiyun int gpio_request(unsigned gpio, const char *label)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun unsigned int port = GPIO_TO_PORT(gpio);
133*4882a593Smuzhiyun if (port >= ARRAY_SIZE(gpio_ports))
134*4882a593Smuzhiyun return -1;
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
gpio_free(unsigned gpio)138*4882a593Smuzhiyun int gpio_free(unsigned gpio)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
gpio_direction_input(unsigned gpio)143*4882a593Smuzhiyun int gpio_direction_input(unsigned gpio)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
gpio_direction_output(unsigned gpio,int value)148*4882a593Smuzhiyun int gpio_direction_output(unsigned gpio, int value)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int ret = gpio_set_value(gpio, value);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (ret < 0)
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun #endif
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun #ifdef CONFIG_DM_GPIO
160*4882a593Smuzhiyun #include <fdtdec.h>
161*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
162*4882a593Smuzhiyun
mxc_gpio_is_output(struct gpio_regs * regs,int offset)163*4882a593Smuzhiyun static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun u32 val;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun val = readl(®s->gpio_dir);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return val & (1 << offset) ? 1 : 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
mxc_gpio_bank_direction(struct gpio_regs * regs,int offset,enum mxc_gpio_direction direction)172*4882a593Smuzhiyun static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
173*4882a593Smuzhiyun enum mxc_gpio_direction direction)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun u32 l;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun l = readl(®s->gpio_dir);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun switch (direction) {
180*4882a593Smuzhiyun case MXC_GPIO_DIRECTION_OUT:
181*4882a593Smuzhiyun l |= 1 << offset;
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun case MXC_GPIO_DIRECTION_IN:
184*4882a593Smuzhiyun l &= ~(1 << offset);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun writel(l, ®s->gpio_dir);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
mxc_gpio_bank_set_value(struct gpio_regs * regs,int offset,int value)189*4882a593Smuzhiyun static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
190*4882a593Smuzhiyun int value)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun u32 l;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun l = readl(®s->gpio_dr);
195*4882a593Smuzhiyun if (value)
196*4882a593Smuzhiyun l |= 1 << offset;
197*4882a593Smuzhiyun else
198*4882a593Smuzhiyun l &= ~(1 << offset);
199*4882a593Smuzhiyun writel(l, ®s->gpio_dr);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
mxc_gpio_bank_get_value(struct gpio_regs * regs,int offset)202*4882a593Smuzhiyun static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun return (readl(®s->gpio_psr) >> offset) & 0x01;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* set GPIO pin 'gpio' as an input */
mxc_gpio_direction_input(struct udevice * dev,unsigned offset)208*4882a593Smuzhiyun static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Configure GPIO direction as input. */
213*4882a593Smuzhiyun mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun return 0;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* set GPIO pin 'gpio' as an output, with polarity 'value' */
mxc_gpio_direction_output(struct udevice * dev,unsigned offset,int value)219*4882a593Smuzhiyun static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
220*4882a593Smuzhiyun int value)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* Configure GPIO output value. */
225*4882a593Smuzhiyun mxc_gpio_bank_set_value(bank->regs, offset, value);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /* Configure GPIO direction as output. */
228*4882a593Smuzhiyun mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /* read GPIO IN value of pin 'gpio' */
mxc_gpio_get_value(struct udevice * dev,unsigned offset)234*4882a593Smuzhiyun static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun return mxc_gpio_bank_get_value(bank->regs, offset);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* write GPIO OUT value to pin 'gpio' */
mxc_gpio_set_value(struct udevice * dev,unsigned offset,int value)242*4882a593Smuzhiyun static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
243*4882a593Smuzhiyun int value)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun mxc_gpio_bank_set_value(bank->regs, offset, value);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
mxc_gpio_get_function(struct udevice * dev,unsigned offset)252*4882a593Smuzhiyun static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* GPIOF_FUNC is not implemented yet */
257*4882a593Smuzhiyun if (mxc_gpio_is_output(bank->regs, offset))
258*4882a593Smuzhiyun return GPIOF_OUTPUT;
259*4882a593Smuzhiyun else
260*4882a593Smuzhiyun return GPIOF_INPUT;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static const struct dm_gpio_ops gpio_mxc_ops = {
264*4882a593Smuzhiyun .direction_input = mxc_gpio_direction_input,
265*4882a593Smuzhiyun .direction_output = mxc_gpio_direction_output,
266*4882a593Smuzhiyun .get_value = mxc_gpio_get_value,
267*4882a593Smuzhiyun .set_value = mxc_gpio_set_value,
268*4882a593Smuzhiyun .get_function = mxc_gpio_get_function,
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
mxc_gpio_probe(struct udevice * dev)271*4882a593Smuzhiyun static int mxc_gpio_probe(struct udevice *dev)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct mxc_bank_info *bank = dev_get_priv(dev);
274*4882a593Smuzhiyun struct mxc_gpio_plat *plat = dev_get_platdata(dev);
275*4882a593Smuzhiyun struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
276*4882a593Smuzhiyun int banknum;
277*4882a593Smuzhiyun char name[18], *str;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun banknum = plat->bank_index;
280*4882a593Smuzhiyun sprintf(name, "GPIO%d_", banknum + 1);
281*4882a593Smuzhiyun str = strdup(name);
282*4882a593Smuzhiyun if (!str)
283*4882a593Smuzhiyun return -ENOMEM;
284*4882a593Smuzhiyun uc_priv->bank_name = str;
285*4882a593Smuzhiyun uc_priv->gpio_count = GPIO_PER_BANK;
286*4882a593Smuzhiyun bank->regs = plat->regs;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return 0;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
mxc_gpio_bind(struct udevice * dev)291*4882a593Smuzhiyun static int mxc_gpio_bind(struct udevice *dev)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct mxc_gpio_plat *plat = dev->platdata;
294*4882a593Smuzhiyun fdt_addr_t addr;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /*
297*4882a593Smuzhiyun * If platdata already exsits, directly return.
298*4882a593Smuzhiyun * Actually only when DT is not supported, platdata
299*4882a593Smuzhiyun * is statically initialized in U_BOOT_DEVICES.Here
300*4882a593Smuzhiyun * will return.
301*4882a593Smuzhiyun */
302*4882a593Smuzhiyun if (plat)
303*4882a593Smuzhiyun return 0;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun addr = devfdt_get_addr(dev);
306*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
307*4882a593Smuzhiyun return -EINVAL;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /*
310*4882a593Smuzhiyun * TODO:
311*4882a593Smuzhiyun * When every board is converted to driver model and DT is supported,
312*4882a593Smuzhiyun * this can be done by auto-alloc feature, but not using calloc
313*4882a593Smuzhiyun * to alloc memory for platdata.
314*4882a593Smuzhiyun */
315*4882a593Smuzhiyun plat = calloc(1, sizeof(*plat));
316*4882a593Smuzhiyun if (!plat)
317*4882a593Smuzhiyun return -ENOMEM;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun plat->regs = (struct gpio_regs *)addr;
320*4882a593Smuzhiyun plat->bank_index = dev->req_seq;
321*4882a593Smuzhiyun dev->platdata = plat;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return 0;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun static const struct udevice_id mxc_gpio_ids[] = {
327*4882a593Smuzhiyun { .compatible = "fsl,imx35-gpio" },
328*4882a593Smuzhiyun { }
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun U_BOOT_DRIVER(gpio_mxc) = {
332*4882a593Smuzhiyun .name = "gpio_mxc",
333*4882a593Smuzhiyun .id = UCLASS_GPIO,
334*4882a593Smuzhiyun .ops = &gpio_mxc_ops,
335*4882a593Smuzhiyun .probe = mxc_gpio_probe,
336*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
337*4882a593Smuzhiyun .of_match = mxc_gpio_ids,
338*4882a593Smuzhiyun .bind = mxc_gpio_bind,
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun #if !CONFIG_IS_ENABLED(OF_CONTROL)
342*4882a593Smuzhiyun static const struct mxc_gpio_plat mxc_plat[] = {
343*4882a593Smuzhiyun { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
344*4882a593Smuzhiyun { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
345*4882a593Smuzhiyun { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
346*4882a593Smuzhiyun #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
347*4882a593Smuzhiyun defined(CONFIG_MX53) || defined(CONFIG_MX6)
348*4882a593Smuzhiyun { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
349*4882a593Smuzhiyun #endif
350*4882a593Smuzhiyun #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
351*4882a593Smuzhiyun { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
352*4882a593Smuzhiyun { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
353*4882a593Smuzhiyun #endif
354*4882a593Smuzhiyun #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
355*4882a593Smuzhiyun { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
356*4882a593Smuzhiyun #endif
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun U_BOOT_DEVICES(mxc_gpios) = {
360*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[0] },
361*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[1] },
362*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[2] },
363*4882a593Smuzhiyun #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
364*4882a593Smuzhiyun defined(CONFIG_MX53) || defined(CONFIG_MX6)
365*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[3] },
366*4882a593Smuzhiyun #endif
367*4882a593Smuzhiyun #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
368*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[4] },
369*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[5] },
370*4882a593Smuzhiyun #endif
371*4882a593Smuzhiyun #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
372*4882a593Smuzhiyun { "gpio_mxc", &mxc_plat[6] },
373*4882a593Smuzhiyun #endif
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun #endif
376*4882a593Smuzhiyun #endif
377