1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/io.h> 11*4882a593Smuzhiyun #include <mvmfp.h> 12*4882a593Smuzhiyun #include <asm/arch/mfp.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * mfp_config 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin 18*4882a593Smuzhiyun * configuration registers to configure each GPIO/Function pin on the 19*4882a593Smuzhiyun * SoC. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * This function reads the array of values for 22*4882a593Smuzhiyun * MFPR_X registers and programms them into respective 23*4882a593Smuzhiyun * Multi-Function Pin registers. 24*4882a593Smuzhiyun * It supports - Alternate Function Selection programming. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * Whereas, 27*4882a593Smuzhiyun * The Configureation value is constructed using MFP() 28*4882a593Smuzhiyun * array consists of 32bit values as defined in MFP(xx,xx..) macro 29*4882a593Smuzhiyun */ mfp_config(u32 * mfp_cfgs)30*4882a593Smuzhiyunvoid mfp_config(u32 *mfp_cfgs) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun u32 *p_mfpr = NULL; 33*4882a593Smuzhiyun u32 cfg_val, val; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun do { 36*4882a593Smuzhiyun cfg_val = *mfp_cfgs++; 37*4882a593Smuzhiyun /* exit if End of configuration table detected */ 38*4882a593Smuzhiyun if (cfg_val == MFP_EOC) 39*4882a593Smuzhiyun break; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun p_mfpr = (u32 *)(MV_MFPR_BASE 42*4882a593Smuzhiyun + MFP_REG_GET_OFFSET(cfg_val)); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Write a mfg register as per configuration */ 45*4882a593Smuzhiyun val = 0; 46*4882a593Smuzhiyun if (cfg_val & MFP_VALUE_MASK) 47*4882a593Smuzhiyun val |= cfg_val & MFP_VALUE_MASK; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun writel(val, p_mfpr); 50*4882a593Smuzhiyun } while (1); 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * perform a read-back of any MFPR register to make sure the 53*4882a593Smuzhiyun * previous writings are finished 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun readl(p_mfpr); 56*4882a593Smuzhiyun } 57