1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * eInfochips Ltd. <www.einfochips.com> 4*4882a593Smuzhiyun * Written-by: Ajay Bhargav <contact@8051projects.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2010 7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __MVGPIO_H__ 13*4882a593Smuzhiyun #define __MVGPIO_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <common.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * GPIO Register map for Marvell SOCs 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun struct gpio_reg { 21*4882a593Smuzhiyun u32 gplr; /* Pin Level Register - 0x0000 */ 22*4882a593Smuzhiyun u32 pad0[2]; 23*4882a593Smuzhiyun u32 gpdr; /* Pin Direction Register - 0x000C */ 24*4882a593Smuzhiyun u32 pad1[2]; 25*4882a593Smuzhiyun u32 gpsr; /* Pin Output Set Register - 0x0018 */ 26*4882a593Smuzhiyun u32 pad2[2]; 27*4882a593Smuzhiyun u32 gpcr; /* Pin Output Clear Register - 0x0024 */ 28*4882a593Smuzhiyun u32 pad3[2]; 29*4882a593Smuzhiyun u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ 30*4882a593Smuzhiyun u32 pad4[2]; 31*4882a593Smuzhiyun u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ 32*4882a593Smuzhiyun u32 pad5[2]; 33*4882a593Smuzhiyun u32 gedr; /* Edge Detect Status Register - 0x0048 */ 34*4882a593Smuzhiyun u32 pad6[2]; 35*4882a593Smuzhiyun u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ 36*4882a593Smuzhiyun u32 pad7[2]; 37*4882a593Smuzhiyun u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ 38*4882a593Smuzhiyun u32 pad8[2]; 39*4882a593Smuzhiyun u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable 40*4882a593Smuzhiyun Register - 0x006C */ 41*4882a593Smuzhiyun u32 pad9[2]; 42*4882a593Smuzhiyun u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable 43*4882a593Smuzhiyun Register - 0x0078 */ 44*4882a593Smuzhiyun u32 pad10[2]; 45*4882a593Smuzhiyun u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable 46*4882a593Smuzhiyun Register - 0x0084 */ 47*4882a593Smuzhiyun u32 pad11[2]; 48*4882a593Smuzhiyun u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable 49*4882a593Smuzhiyun Register - 0x0090 */ 50*4882a593Smuzhiyun u32 pad12[2]; 51*4882a593Smuzhiyun u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* __MVGPIO_H__ */ 55