1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <asm/gpio.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define MVEBU_GPIOS_PER_BANK 32
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct mvebu_gpio_regs {
18*4882a593Smuzhiyun u32 data_out;
19*4882a593Smuzhiyun u32 io_conf;
20*4882a593Smuzhiyun u32 blink_en;
21*4882a593Smuzhiyun u32 in_pol;
22*4882a593Smuzhiyun u32 data_in;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct mvebu_gpio_priv {
26*4882a593Smuzhiyun struct mvebu_gpio_regs *regs;
27*4882a593Smuzhiyun char name[2];
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
mvebu_gpio_direction_input(struct udevice * dev,unsigned int gpio)30*4882a593Smuzhiyun static int mvebu_gpio_direction_input(struct udevice *dev, unsigned int gpio)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
33*4882a593Smuzhiyun struct mvebu_gpio_regs *regs = priv->regs;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun setbits_le32(®s->io_conf, BIT(gpio));
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
mvebu_gpio_direction_output(struct udevice * dev,unsigned gpio,int value)40*4882a593Smuzhiyun static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio,
41*4882a593Smuzhiyun int value)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
44*4882a593Smuzhiyun struct mvebu_gpio_regs *regs = priv->regs;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (value)
47*4882a593Smuzhiyun setbits_le32(®s->data_out, BIT(gpio));
48*4882a593Smuzhiyun else
49*4882a593Smuzhiyun clrbits_le32(®s->data_out, BIT(gpio));
50*4882a593Smuzhiyun clrbits_le32(®s->io_conf, BIT(gpio));
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
mvebu_gpio_get_function(struct udevice * dev,unsigned gpio)55*4882a593Smuzhiyun static int mvebu_gpio_get_function(struct udevice *dev, unsigned gpio)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
58*4882a593Smuzhiyun struct mvebu_gpio_regs *regs = priv->regs;
59*4882a593Smuzhiyun u32 val;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun val = readl(®s->io_conf) & BIT(gpio);
62*4882a593Smuzhiyun if (val)
63*4882a593Smuzhiyun return GPIOF_INPUT;
64*4882a593Smuzhiyun else
65*4882a593Smuzhiyun return GPIOF_OUTPUT;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
mvebu_gpio_set_value(struct udevice * dev,unsigned gpio,int value)68*4882a593Smuzhiyun static int mvebu_gpio_set_value(struct udevice *dev, unsigned gpio,
69*4882a593Smuzhiyun int value)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
72*4882a593Smuzhiyun struct mvebu_gpio_regs *regs = priv->regs;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (value)
75*4882a593Smuzhiyun setbits_le32(®s->data_out, BIT(gpio));
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun clrbits_le32(®s->data_out, BIT(gpio));
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
mvebu_gpio_get_value(struct udevice * dev,unsigned gpio)82*4882a593Smuzhiyun static int mvebu_gpio_get_value(struct udevice *dev, unsigned gpio)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
85*4882a593Smuzhiyun struct mvebu_gpio_regs *regs = priv->regs;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return !!(readl(®s->data_in) & BIT(gpio));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
mvebu_gpio_probe(struct udevice * dev)90*4882a593Smuzhiyun static int mvebu_gpio_probe(struct udevice *dev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
93*4882a593Smuzhiyun struct mvebu_gpio_priv *priv = dev_get_priv(dev);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun priv->regs = (struct mvebu_gpio_regs *)devfdt_get_addr(dev);
96*4882a593Smuzhiyun uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK;
97*4882a593Smuzhiyun priv->name[0] = 'A' + dev->req_seq;
98*4882a593Smuzhiyun uc_priv->bank_name = priv->name;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct dm_gpio_ops mvebu_gpio_ops = {
104*4882a593Smuzhiyun .direction_input = mvebu_gpio_direction_input,
105*4882a593Smuzhiyun .direction_output = mvebu_gpio_direction_output,
106*4882a593Smuzhiyun .get_function = mvebu_gpio_get_function,
107*4882a593Smuzhiyun .get_value = mvebu_gpio_get_value,
108*4882a593Smuzhiyun .set_value = mvebu_gpio_set_value,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static const struct udevice_id mvebu_gpio_ids[] = {
112*4882a593Smuzhiyun { .compatible = "marvell,orion-gpio" },
113*4882a593Smuzhiyun { }
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun U_BOOT_DRIVER(gpio_mvebu) = {
117*4882a593Smuzhiyun .name = "gpio_mvebu",
118*4882a593Smuzhiyun .id = UCLASS_GPIO,
119*4882a593Smuzhiyun .of_match = mvebu_gpio_ids,
120*4882a593Smuzhiyun .ops = &mvebu_gpio_ops,
121*4882a593Smuzhiyun .probe = mvebu_gpio_probe,
122*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct mvebu_gpio_priv),
123*4882a593Smuzhiyun };
124