xref: /OK3568_Linux_fs/u-boot/drivers/gpio/mpc85xx_gpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2016
3*4882a593Smuzhiyun  * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright 2010 eXMeritus, A Boeing Company
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <dm.h>
14*4882a593Smuzhiyun #include <asm/gpio.h>
15*4882a593Smuzhiyun #include <mapmem.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun struct ccsr_gpio {
20*4882a593Smuzhiyun 	u32	gpdir;
21*4882a593Smuzhiyun 	u32	gpodr;
22*4882a593Smuzhiyun 	u32	gpdat;
23*4882a593Smuzhiyun 	u32	gpier;
24*4882a593Smuzhiyun 	u32	gpimr;
25*4882a593Smuzhiyun 	u32	gpicr;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct mpc85xx_gpio_data {
29*4882a593Smuzhiyun 	/* The bank's register base in memory */
30*4882a593Smuzhiyun 	struct ccsr_gpio __iomem *base;
31*4882a593Smuzhiyun 	/* The address of the registers; used to identify the bank */
32*4882a593Smuzhiyun 	ulong addr;
33*4882a593Smuzhiyun 	/* The GPIO count of the bank */
34*4882a593Smuzhiyun 	uint gpio_count;
35*4882a593Smuzhiyun 	/* The GPDAT register cannot be used to determine the value of output
36*4882a593Smuzhiyun 	 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
37*4882a593Smuzhiyun 	 * for output pins */
38*4882a593Smuzhiyun 	u32 dat_shadow;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
gpio_mask(unsigned gpio)41*4882a593Smuzhiyun inline u32 gpio_mask(unsigned gpio) {
42*4882a593Smuzhiyun 	return (1U << (31 - (gpio)));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
mpc85xx_gpio_get_val(struct ccsr_gpio * base,u32 mask)45*4882a593Smuzhiyun static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	return in_be32(&base->gpdat) & mask;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
mpc85xx_gpio_get_dir(struct ccsr_gpio * base,u32 mask)50*4882a593Smuzhiyun static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	return in_be32(&base->gpdir) & mask;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
mpc85xx_gpio_set_in(struct ccsr_gpio * base,u32 gpios)55*4882a593Smuzhiyun static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	clrbits_be32(&base->gpdat, gpios);
58*4882a593Smuzhiyun 	/* GPDIR register 0 -> input */
59*4882a593Smuzhiyun 	clrbits_be32(&base->gpdir, gpios);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
mpc85xx_gpio_set_low(struct ccsr_gpio * base,u32 gpios)62*4882a593Smuzhiyun static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	clrbits_be32(&base->gpdat, gpios);
65*4882a593Smuzhiyun 	/* GPDIR register 1 -> output */
66*4882a593Smuzhiyun 	setbits_be32(&base->gpdir, gpios);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
mpc85xx_gpio_set_high(struct ccsr_gpio * base,u32 gpios)69*4882a593Smuzhiyun static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	setbits_be32(&base->gpdat, gpios);
72*4882a593Smuzhiyun 	/* GPDIR register 1 -> output */
73*4882a593Smuzhiyun 	setbits_be32(&base->gpdir, gpios);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
mpc85xx_gpio_open_drain_val(struct ccsr_gpio * base,u32 mask)76*4882a593Smuzhiyun static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	return in_be32(&base->gpodr) & mask;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
mpc85xx_gpio_open_drain_on(struct ccsr_gpio * base,u32 gpios)81*4882a593Smuzhiyun static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
82*4882a593Smuzhiyun 					      gpios)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	/* GPODR register 1 -> open drain on */
85*4882a593Smuzhiyun 	setbits_be32(&base->gpodr, gpios);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
mpc85xx_gpio_open_drain_off(struct ccsr_gpio * base,u32 gpios)88*4882a593Smuzhiyun static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
89*4882a593Smuzhiyun 					       u32 gpios)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	/* GPODR register 0 -> open drain off (actively driven) */
92*4882a593Smuzhiyun 	clrbits_be32(&base->gpodr, gpios);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
mpc85xx_gpio_direction_input(struct udevice * dev,unsigned gpio)95*4882a593Smuzhiyun static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
100*4882a593Smuzhiyun 	return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
mpc85xx_gpio_set_value(struct udevice * dev,unsigned gpio,int value)103*4882a593Smuzhiyun static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
104*4882a593Smuzhiyun 				  int value)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	if (value) {
109*4882a593Smuzhiyun 		data->dat_shadow |= gpio_mask(gpio);
110*4882a593Smuzhiyun 		mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
111*4882a593Smuzhiyun 	} else {
112*4882a593Smuzhiyun 		data->dat_shadow &= ~gpio_mask(gpio);
113*4882a593Smuzhiyun 		mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
114*4882a593Smuzhiyun 	}
115*4882a593Smuzhiyun 	return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
mpc85xx_gpio_direction_output(struct udevice * dev,unsigned gpio,int value)118*4882a593Smuzhiyun static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
119*4882a593Smuzhiyun 					 int value)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	return mpc85xx_gpio_set_value(dev, gpio, value);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
mpc85xx_gpio_get_value(struct udevice * dev,unsigned gpio)124*4882a593Smuzhiyun static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
129*4882a593Smuzhiyun 		/* Output -> use shadowed value */
130*4882a593Smuzhiyun 		return !!(data->dat_shadow & gpio_mask(gpio));
131*4882a593Smuzhiyun 	} else {
132*4882a593Smuzhiyun 		/* Input -> read value from GPDAT register */
133*4882a593Smuzhiyun 		return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
mpc85xx_gpio_get_open_drain(struct udevice * dev,unsigned gpio)137*4882a593Smuzhiyun static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
mpc85xx_gpio_set_open_drain(struct udevice * dev,unsigned gpio,int value)144*4882a593Smuzhiyun static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
145*4882a593Smuzhiyun 				       int value)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	if (value) {
150*4882a593Smuzhiyun 		mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
151*4882a593Smuzhiyun 	} else {
152*4882a593Smuzhiyun 		mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 	return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
mpc85xx_gpio_get_function(struct udevice * dev,unsigned gpio)157*4882a593Smuzhiyun static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
160*4882a593Smuzhiyun 	int dir;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
163*4882a593Smuzhiyun 	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(OF_CONTROL)
mpc85xx_gpio_ofdata_to_platdata(struct udevice * dev)167*4882a593Smuzhiyun static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
168*4882a593Smuzhiyun 	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
169*4882a593Smuzhiyun 	fdt_addr_t addr;
170*4882a593Smuzhiyun 	fdt_size_t size;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
173*4882a593Smuzhiyun 			dev_of_offset(dev), "reg", 0, &size, false);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	plat->addr = addr;
176*4882a593Smuzhiyun 	plat->size = size;
177*4882a593Smuzhiyun 	plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
178*4882a593Smuzhiyun 				      "ngpios", 32);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun #endif
183*4882a593Smuzhiyun 
mpc85xx_gpio_platdata_to_priv(struct udevice * dev)184*4882a593Smuzhiyun static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
187*4882a593Smuzhiyun 	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
188*4882a593Smuzhiyun 	unsigned long size = plat->size;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	if (size == 0)
191*4882a593Smuzhiyun 		size = 0x100;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	priv->addr = plat->addr;
194*4882a593Smuzhiyun 	priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	if (!priv->base)
197*4882a593Smuzhiyun 		return -ENOMEM;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	priv->gpio_count = plat->ngpios;
200*4882a593Smuzhiyun 	priv->dat_shadow = 0;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
mpc85xx_gpio_probe(struct udevice * dev)205*4882a593Smuzhiyun static int mpc85xx_gpio_probe(struct udevice *dev)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
208*4882a593Smuzhiyun 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
209*4882a593Smuzhiyun 	char name[32], *str;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	mpc85xx_gpio_platdata_to_priv(dev);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
214*4882a593Smuzhiyun 	str = strdup(name);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (!str)
217*4882a593Smuzhiyun 		return -ENOMEM;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	uc_priv->bank_name = str;
220*4882a593Smuzhiyun 	uc_priv->gpio_count = data->gpio_count;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun static const struct dm_gpio_ops gpio_mpc85xx_ops = {
226*4882a593Smuzhiyun 	.direction_input	= mpc85xx_gpio_direction_input,
227*4882a593Smuzhiyun 	.direction_output	= mpc85xx_gpio_direction_output,
228*4882a593Smuzhiyun 	.get_value		= mpc85xx_gpio_get_value,
229*4882a593Smuzhiyun 	.set_value		= mpc85xx_gpio_set_value,
230*4882a593Smuzhiyun 	.get_open_drain		= mpc85xx_gpio_get_open_drain,
231*4882a593Smuzhiyun 	.set_open_drain		= mpc85xx_gpio_set_open_drain,
232*4882a593Smuzhiyun 	.get_function 		= mpc85xx_gpio_get_function,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct udevice_id mpc85xx_gpio_ids[] = {
236*4882a593Smuzhiyun 	{ .compatible = "fsl,pq3-gpio" },
237*4882a593Smuzhiyun 	{ /* sentinel */ }
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun U_BOOT_DRIVER(gpio_mpc85xx) = {
241*4882a593Smuzhiyun 	.name	= "gpio_mpc85xx",
242*4882a593Smuzhiyun 	.id	= UCLASS_GPIO,
243*4882a593Smuzhiyun 	.ops	= &gpio_mpc85xx_ops,
244*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(OF_CONTROL)
245*4882a593Smuzhiyun 	.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
246*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
247*4882a593Smuzhiyun 	.of_match = mpc85xx_gpio_ids,
248*4882a593Smuzhiyun #endif
249*4882a593Smuzhiyun 	.probe	= mpc85xx_gpio_probe,
250*4882a593Smuzhiyun 	.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
251*4882a593Smuzhiyun };
252