1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 Vikram Narayananan
3*4882a593Smuzhiyun * <vikram186@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <asm/gpio.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <fdtdec.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct bcm2835_gpios {
16*4882a593Smuzhiyun struct bcm2835_gpio_regs *reg;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
bcm2835_gpio_direction_input(struct udevice * dev,unsigned gpio)19*4882a593Smuzhiyun static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct bcm2835_gpios *gpios = dev_get_priv(dev);
22*4882a593Smuzhiyun unsigned val;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
25*4882a593Smuzhiyun val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
26*4882a593Smuzhiyun val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
27*4882a593Smuzhiyun writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
bcm2835_gpio_direction_output(struct udevice * dev,unsigned gpio,int value)32*4882a593Smuzhiyun static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio,
33*4882a593Smuzhiyun int value)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct bcm2835_gpios *gpios = dev_get_priv(dev);
36*4882a593Smuzhiyun unsigned val;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun gpio_set_value(gpio, value);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
41*4882a593Smuzhiyun val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
42*4882a593Smuzhiyun val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
43*4882a593Smuzhiyun writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
bcm2835_get_value(const struct bcm2835_gpios * gpios,unsigned gpio)48*4882a593Smuzhiyun static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun unsigned val;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
bcm2835_gpio_get_value(struct udevice * dev,unsigned gpio)57*4882a593Smuzhiyun static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun const struct bcm2835_gpios *gpios = dev_get_priv(dev);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return bcm2835_get_value(gpios, gpio);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
bcm2835_gpio_set_value(struct udevice * dev,unsigned gpio,int value)64*4882a593Smuzhiyun static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio,
65*4882a593Smuzhiyun int value)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct bcm2835_gpios *gpios = dev_get_priv(dev);
68*4882a593Smuzhiyun u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
71*4882a593Smuzhiyun &output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
bcm2835_gpio_get_func_id(struct udevice * dev,unsigned gpio)76*4882a593Smuzhiyun int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct bcm2835_gpios *gpios = dev_get_priv(dev);
79*4882a593Smuzhiyun u32 val;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
bcm2835_gpio_get_function(struct udevice * dev,unsigned offset)86*4882a593Smuzhiyun static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int funcid = bcm2835_gpio_get_func_id(dev, offset);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun switch (funcid) {
91*4882a593Smuzhiyun case BCM2835_GPIO_OUTPUT:
92*4882a593Smuzhiyun return GPIOF_OUTPUT;
93*4882a593Smuzhiyun case BCM2835_GPIO_INPUT:
94*4882a593Smuzhiyun return GPIOF_INPUT;
95*4882a593Smuzhiyun default:
96*4882a593Smuzhiyun return GPIOF_FUNC;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct dm_gpio_ops gpio_bcm2835_ops = {
102*4882a593Smuzhiyun .direction_input = bcm2835_gpio_direction_input,
103*4882a593Smuzhiyun .direction_output = bcm2835_gpio_direction_output,
104*4882a593Smuzhiyun .get_value = bcm2835_gpio_get_value,
105*4882a593Smuzhiyun .set_value = bcm2835_gpio_set_value,
106*4882a593Smuzhiyun .get_function = bcm2835_gpio_get_function,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
bcm2835_gpio_probe(struct udevice * dev)109*4882a593Smuzhiyun static int bcm2835_gpio_probe(struct udevice *dev)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct bcm2835_gpios *gpios = dev_get_priv(dev);
112*4882a593Smuzhiyun struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
113*4882a593Smuzhiyun struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun uc_priv->bank_name = "GPIO";
116*4882a593Smuzhiyun uc_priv->gpio_count = BCM2835_GPIO_COUNT;
117*4882a593Smuzhiyun gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(OF_CONTROL)
123*4882a593Smuzhiyun static const struct udevice_id bcm2835_gpio_id[] = {
124*4882a593Smuzhiyun {.compatible = "brcm,bcm2835-gpio"},
125*4882a593Smuzhiyun {}
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
bcm2835_gpio_ofdata_to_platdata(struct udevice * dev)128*4882a593Smuzhiyun static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
131*4882a593Smuzhiyun fdt_addr_t addr;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun addr = devfdt_get_addr(dev);
134*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
135*4882a593Smuzhiyun return -EINVAL;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun plat->base = addr;
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun U_BOOT_DRIVER(gpio_bcm2835) = {
143*4882a593Smuzhiyun .name = "gpio_bcm2835",
144*4882a593Smuzhiyun .id = UCLASS_GPIO,
145*4882a593Smuzhiyun .of_match = of_match_ptr(bcm2835_gpio_id),
146*4882a593Smuzhiyun .ofdata_to_platdata = of_match_ptr(bcm2835_gpio_ofdata_to_platdata),
147*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct bcm2835_gpio_platdata),
148*4882a593Smuzhiyun .ops = &gpio_bcm2835_ops,
149*4882a593Smuzhiyun .probe = bcm2835_gpio_probe,
150*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
151*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
152*4882a593Smuzhiyun };
153