xref: /OK3568_Linux_fs/u-boot/drivers/gpio/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun#
2*4882a593Smuzhiyun# GPIO infrastructure and drivers
3*4882a593Smuzhiyun#
4*4882a593Smuzhiyun
5*4882a593Smuzhiyunmenu "GPIO Support"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyunconfig DM_GPIO
8*4882a593Smuzhiyun	bool "Enable Driver Model for GPIO drivers"
9*4882a593Smuzhiyun	depends on DM
10*4882a593Smuzhiyun	help
11*4882a593Smuzhiyun	  Enable driver model for GPIO access. The standard GPIO
12*4882a593Smuzhiyun	  interface (gpio_get_value(), etc.) is then implemented by
13*4882a593Smuzhiyun	  the GPIO uclass. Drivers provide methods to query the
14*4882a593Smuzhiyun	  particular GPIOs that they provide. The uclass interface
15*4882a593Smuzhiyun	  is defined in include/asm-generic/gpio.h.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunconfig GPIO_HOG
18*4882a593Smuzhiyun	bool "Enable GPIO hog support"
19*4882a593Smuzhiyun	depends on DM_GPIO
20*4882a593Smuzhiyun	default n
21*4882a593Smuzhiyun	help
22*4882a593Smuzhiyun	  Enable gpio hog support
23*4882a593Smuzhiyun	  The GPIO chip may contain GPIO hog definitions. GPIO hogging
24*4882a593Smuzhiyun	  is a mechanism providing automatic GPIO request and config-
25*4882a593Smuzhiyun	  uration as part of the gpio-controller's driver probe function.
26*4882a593Smuzhiyun
27*4882a593Smuzhiyunconfig GPIO_NO_UC_FLAG_SEQ_ALIAS
28*4882a593Smuzhiyun	bool "Disable GPIO uclass sequence themselves with aliases"
29*4882a593Smuzhiyun	depends on USING_KERNEL_DTB
30*4882a593Smuzhiyun	default n
31*4882a593Smuzhiyun	help
32*4882a593Smuzhiyun	  Disable GPIO uclass sequence, this is a workaround when kernel
33*4882a593Smuzhiyun	  dtb feature is enabled. Avoid gpio device probe failed when
34*4882a593Smuzhiyun	  alloc req_seq both for gpio devices from U-Boot and kernel dtb.
35*4882a593Smuzhiyun
36*4882a593Smuzhiyunconfig ALTERA_PIO
37*4882a593Smuzhiyun	bool "Altera PIO driver"
38*4882a593Smuzhiyun	depends on DM_GPIO
39*4882a593Smuzhiyun	help
40*4882a593Smuzhiyun	  Select this to enable PIO for Altera devices. Please find
41*4882a593Smuzhiyun	  details on the "Embedded Peripherals IP User Guide" of Altera.
42*4882a593Smuzhiyun
43*4882a593Smuzhiyunconfig BCM6345_GPIO
44*4882a593Smuzhiyun	bool "BCM6345 GPIO driver"
45*4882a593Smuzhiyun	depends on DM_GPIO && ARCH_BMIPS
46*4882a593Smuzhiyun	help
47*4882a593Smuzhiyun	  This driver supports the GPIO banks on BCM6345 SoCs.
48*4882a593Smuzhiyun
49*4882a593Smuzhiyunconfig DWAPB_GPIO
50*4882a593Smuzhiyun	bool "DWAPB GPIO driver"
51*4882a593Smuzhiyun	depends on DM && DM_GPIO
52*4882a593Smuzhiyun	default n
53*4882a593Smuzhiyun	help
54*4882a593Smuzhiyun	  Support for the Designware APB GPIO driver.
55*4882a593Smuzhiyun
56*4882a593Smuzhiyunconfig AT91_GPIO
57*4882a593Smuzhiyun	bool "AT91 PIO GPIO driver"
58*4882a593Smuzhiyun	depends on DM_GPIO
59*4882a593Smuzhiyun	default n
60*4882a593Smuzhiyun	help
61*4882a593Smuzhiyun	  Say yes here to select AT91 PIO GPIO driver. AT91 PIO
62*4882a593Smuzhiyun	  controller manages up to 32 fully programmable input/output
63*4882a593Smuzhiyun	  lines. Each I/O line may be dedicated as a general-purpose
64*4882a593Smuzhiyun	  I/O or be assigned to a function of an embedded peripheral.
65*4882a593Smuzhiyun	  The assignment to a function of an embedded peripheral is
66*4882a593Smuzhiyun	  the responsibility of AT91 Pinctrl driver. This driver is
67*4882a593Smuzhiyun	  responsible for the general-purpose I/O.
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunconfig ATMEL_PIO4
70*4882a593Smuzhiyun	bool "ATMEL PIO4 driver"
71*4882a593Smuzhiyun	depends on DM_GPIO
72*4882a593Smuzhiyun	default n
73*4882a593Smuzhiyun	help
74*4882a593Smuzhiyun	  Say yes here to support the Atmel PIO4 driver.
75*4882a593Smuzhiyun	  The PIO4 is new version of Atmel PIO controller, which manages
76*4882a593Smuzhiyun	  up to 128 fully programmable input/output lines. Each I/O line
77*4882a593Smuzhiyun	  may be dedicated as a general purpose I/O or be assigned to
78*4882a593Smuzhiyun	  a function of an embedded peripheral.
79*4882a593Smuzhiyun
80*4882a593Smuzhiyunconfig INTEL_BROADWELL_GPIO
81*4882a593Smuzhiyun	bool "Intel Broadwell GPIO driver"
82*4882a593Smuzhiyun	depends on DM
83*4882a593Smuzhiyun	help
84*4882a593Smuzhiyun	  This driver supports Broadwell U devices which have an expanded
85*4882a593Smuzhiyun	  GPIO feature set. The difference is large enough to merit a separate
86*4882a593Smuzhiyun	  driver from the common Intel ICH6 driver. It supports a total of
87*4882a593Smuzhiyun	  95 GPIOs which can be configured from the device tree.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyunconfig INTEL_ICH6_GPIO
90*4882a593Smuzhiyun	bool "Intel ICH6 compatible legacy GPIO driver"
91*4882a593Smuzhiyun	depends on DM_GPIO
92*4882a593Smuzhiyun	help
93*4882a593Smuzhiyun	  Say yes here to select Intel ICH6 compatible legacy GPIO driver.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyunconfig IMX_RGPIO2P
96*4882a593Smuzhiyun	bool "i.MX7ULP RGPIO2P driver"
97*4882a593Smuzhiyun	depends on DM
98*4882a593Smuzhiyun	default n
99*4882a593Smuzhiyun	help
100*4882a593Smuzhiyun	  This driver supports i.MX7ULP Rapid GPIO2P controller.
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunconfig LPC32XX_GPIO
103*4882a593Smuzhiyun	bool "LPC32XX GPIO driver"
104*4882a593Smuzhiyun	depends on DM
105*4882a593Smuzhiyun	default n
106*4882a593Smuzhiyun	help
107*4882a593Smuzhiyun	  Support for the LPC32XX GPIO driver.
108*4882a593Smuzhiyun
109*4882a593Smuzhiyunconfig MSM_GPIO
110*4882a593Smuzhiyun	bool "Qualcomm GPIO driver"
111*4882a593Smuzhiyun	depends on DM_GPIO
112*4882a593Smuzhiyun	default n
113*4882a593Smuzhiyun	help
114*4882a593Smuzhiyun	  Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
115*4882a593Smuzhiyun	  This controller have single bank (default name "soc"), every
116*4882a593Smuzhiyun	  gpio has it's own set of registers.
117*4882a593Smuzhiyun	  Only simple GPIO operations are supported (get/set, change of
118*4882a593Smuzhiyun	  direction and checking pin function).
119*4882a593Smuzhiyun	  Supported devices:
120*4882a593Smuzhiyun	  - APQ8016
121*4882a593Smuzhiyun	  - MSM8916
122*4882a593Smuzhiyun
123*4882a593Smuzhiyunconfig OMAP_GPIO
124*4882a593Smuzhiyun	bool "TI OMAP GPIO driver"
125*4882a593Smuzhiyun	depends on ARCH_OMAP2PLUS
126*4882a593Smuzhiyun	default y
127*4882a593Smuzhiyun	help
128*4882a593Smuzhiyun	  Support GPIO controllers on the TI OMAP3/4/5 and related (such as
129*4882a593Smuzhiyun	  AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs.
130*4882a593Smuzhiyun
131*4882a593Smuzhiyunconfig CMD_PCA953X
132*4882a593Smuzhiyun	bool "Enable the pca953x command"
133*4882a593Smuzhiyun	help
134*4882a593Smuzhiyun	  Deprecated: This should be converted to driver model.
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	  This command provides access to a pca953x GPIO device using the
137*4882a593Smuzhiyun	  legacy GPIO interface. Several subcommands are provided which mirror
138*4882a593Smuzhiyun	  the standard 'gpio' command. It should use that instead.
139*4882a593Smuzhiyun
140*4882a593Smuzhiyunconfig PM8916_GPIO
141*4882a593Smuzhiyun	bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
142*4882a593Smuzhiyun	depends on DM_GPIO && PMIC_PM8916
143*4882a593Smuzhiyun	help
144*4882a593Smuzhiyun	  Support for GPIO pins and power/reset buttons found on
145*4882a593Smuzhiyun	  Qualcomm PM8916 PMIC.
146*4882a593Smuzhiyun	  Default name for GPIO bank is "pm8916".
147*4882a593Smuzhiyun	  Power and reset buttons are placed in "pm8916_key" bank and
148*4882a593Smuzhiyun          have gpio numbers 0 and 1 respectively.
149*4882a593Smuzhiyun
150*4882a593Smuzhiyunconfig PCF8575_GPIO
151*4882a593Smuzhiyun	bool "PCF8575 I2C GPIO Expander driver"
152*4882a593Smuzhiyun	depends on DM_GPIO && DM_I2C
153*4882a593Smuzhiyun	help
154*4882a593Smuzhiyun	 Support for PCF8575 I2C 16-bit GPIO expander. Most of these
155*4882a593Smuzhiyun	 chips are from NXP and TI.
156*4882a593Smuzhiyun
157*4882a593Smuzhiyunconfig ROCKCHIP_GPIO
158*4882a593Smuzhiyun	bool "Rockchip GPIO driver"
159*4882a593Smuzhiyun	depends on DM_GPIO
160*4882a593Smuzhiyun	help
161*4882a593Smuzhiyun	  Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
162*4882a593Smuzhiyun	  a number of banks (different for each SoC type) each with 32 GPIOs.
163*4882a593Smuzhiyun	  The GPIOs for a device are defined in the device tree with one node
164*4882a593Smuzhiyun	  for each bank.
165*4882a593Smuzhiyun
166*4882a593Smuzhiyunconfig ROCKCHIP_GPIO_V2
167*4882a593Smuzhiyun	bool "Rockchip GPIO driver version 2.0"
168*4882a593Smuzhiyun	depends on ROCKCHIP_GPIO
169*4882a593Smuzhiyun	default n
170*4882a593Smuzhiyun	help
171*4882a593Smuzhiyun	  Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
172*4882a593Smuzhiyun	  a number of banks (different for each SoC type) each with 32 GPIOs.
173*4882a593Smuzhiyun	  The GPIOs for a device are defined in the device tree with one node
174*4882a593Smuzhiyun	  for each bank.
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	  Support version 2.0 GPIO controller, which support write enable bits
177*4882a593Smuzhiyun	  for some registers, such as dr, ddr.
178*4882a593Smuzhiyun
179*4882a593Smuzhiyunconfig SANDBOX_GPIO
180*4882a593Smuzhiyun	bool "Enable sandbox GPIO driver"
181*4882a593Smuzhiyun	depends on SANDBOX && DM && DM_GPIO
182*4882a593Smuzhiyun	help
183*4882a593Smuzhiyun	  This driver supports some simulated GPIOs which can be adjusted
184*4882a593Smuzhiyun	  using 'back door' functions like sandbox_gpio_set_value(). Then the
185*4882a593Smuzhiyun	  GPIOs can be inspected through the normal get_get_value()
186*4882a593Smuzhiyun	  interface. The purpose of this is to allow GPIOs to be used as
187*4882a593Smuzhiyun	  normal in sandbox, perhaps with test code actually driving the
188*4882a593Smuzhiyun	  behaviour of those GPIOs.
189*4882a593Smuzhiyun
190*4882a593Smuzhiyunconfig SANDBOX_GPIO_COUNT
191*4882a593Smuzhiyun	int "Number of sandbox GPIOs"
192*4882a593Smuzhiyun	depends on SANDBOX_GPIO
193*4882a593Smuzhiyun	default 128
194*4882a593Smuzhiyun	help
195*4882a593Smuzhiyun	  The sandbox driver can support any number of GPIOs. Generally these
196*4882a593Smuzhiyun	  are specified using the device tree. But you can also have a number
197*4882a593Smuzhiyun	  of 'anonymous' GPIOs that do not belong to any device or bank.
198*4882a593Smuzhiyun	  Select a suitable value depending on your needs.
199*4882a593Smuzhiyun
200*4882a593Smuzhiyunconfig CMD_TCA642X
201*4882a593Smuzhiyun	bool "tca642x - Command to access tca642x state"
202*4882a593Smuzhiyun	help
203*4882a593Smuzhiyun	  DEPRECATED - This needs conversion to driver model
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	  This provides a way to looking at the pin state of this device.
206*4882a593Smuzhiyun	  This mirrors the 'gpio' command and that should be used in preference
207*4882a593Smuzhiyun	  to custom code.
208*4882a593Smuzhiyun
209*4882a593Smuzhiyunconfig TEGRA_GPIO
210*4882a593Smuzhiyun	bool "Tegra20..210 GPIO driver"
211*4882a593Smuzhiyun	depends on DM_GPIO
212*4882a593Smuzhiyun	help
213*4882a593Smuzhiyun	  Support for the GPIO controller contained in NVIDIA Tegra20 through
214*4882a593Smuzhiyun	  Tegra210.
215*4882a593Smuzhiyun
216*4882a593Smuzhiyunconfig TEGRA186_GPIO
217*4882a593Smuzhiyun	bool "Tegra186 GPIO driver"
218*4882a593Smuzhiyun	depends on DM_GPIO
219*4882a593Smuzhiyun	help
220*4882a593Smuzhiyun	  Support for the GPIO controller contained in NVIDIA Tegra186. This
221*4882a593Smuzhiyun	  covers both the "main" and "AON" controller instances, even though
222*4882a593Smuzhiyun	  they have slightly different register layout.
223*4882a593Smuzhiyun
224*4882a593Smuzhiyunconfig GPIO_UNIPHIER
225*4882a593Smuzhiyun	bool "UniPhier GPIO"
226*4882a593Smuzhiyun	depends on ARCH_UNIPHIER
227*4882a593Smuzhiyun	help
228*4882a593Smuzhiyun	  Say yes here to support UniPhier GPIOs.
229*4882a593Smuzhiyun
230*4882a593Smuzhiyunconfig VYBRID_GPIO
231*4882a593Smuzhiyun	bool "Vybrid GPIO driver"
232*4882a593Smuzhiyun	depends on DM
233*4882a593Smuzhiyun	default n
234*4882a593Smuzhiyun	help
235*4882a593Smuzhiyun	  Say yes here to support Vybrid vf610 GPIOs.
236*4882a593Smuzhiyun
237*4882a593Smuzhiyunconfig PIC32_GPIO
238*4882a593Smuzhiyun	bool "Microchip PIC32 GPIO driver"
239*4882a593Smuzhiyun	depends on DM_GPIO && MACH_PIC32
240*4882a593Smuzhiyun	default y
241*4882a593Smuzhiyun	help
242*4882a593Smuzhiyun	  Say yes here to support Microchip PIC32 GPIOs.
243*4882a593Smuzhiyun
244*4882a593Smuzhiyunconfig STM32F7_GPIO
245*4882a593Smuzhiyun	bool "ST STM32 GPIO driver"
246*4882a593Smuzhiyun	depends on DM_GPIO && STM32
247*4882a593Smuzhiyun	default y
248*4882a593Smuzhiyun	help
249*4882a593Smuzhiyun	  Device model driver support for STM32 GPIO controller. It should be
250*4882a593Smuzhiyun	  usable on many stm32 families like stm32f4 & stm32H7.
251*4882a593Smuzhiyun	  Tested on STM32F7.
252*4882a593Smuzhiyun
253*4882a593Smuzhiyunconfig MVEBU_GPIO
254*4882a593Smuzhiyun	bool "Marvell MVEBU GPIO driver"
255*4882a593Smuzhiyun	depends on DM_GPIO && ARCH_MVEBU
256*4882a593Smuzhiyun	default y
257*4882a593Smuzhiyun	help
258*4882a593Smuzhiyun	  Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
259*4882a593Smuzhiyun
260*4882a593Smuzhiyunconfig ZYNQ_GPIO
261*4882a593Smuzhiyun	bool "Zynq GPIO driver"
262*4882a593Smuzhiyun	depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
263*4882a593Smuzhiyun	default y
264*4882a593Smuzhiyun	help
265*4882a593Smuzhiyun	  Supports GPIO access on Zynq SoC.
266*4882a593Smuzhiyun
267*4882a593Smuzhiyunconfig DM_74X164
268*4882a593Smuzhiyun	bool "74x164 serial-in/parallel-out 8-bits shift register"
269*4882a593Smuzhiyun	depends on DM_GPIO
270*4882a593Smuzhiyun	help
271*4882a593Smuzhiyun	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs
272*4882a593Smuzhiyun	  shift registers, such as 74lv165, 74hc595.
273*4882a593Smuzhiyun	  This driver can be used to provide access to more gpio outputs.
274*4882a593Smuzhiyun
275*4882a593Smuzhiyunconfig DM_PCA953X
276*4882a593Smuzhiyun	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
277*4882a593Smuzhiyun	depends on DM_GPIO
278*4882a593Smuzhiyun	help
279*4882a593Smuzhiyun	  Say yes here to provide access to several register-oriented
280*4882a593Smuzhiyun	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
281*4882a593Smuzhiyun	  models include:
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	  4 bits:	pca9536, pca9537
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
286*4882a593Smuzhiyun			pca9556, pca9557, pca9574, tca6408, xra1202
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
289*4882a593Smuzhiyun			tca6416
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	  24 bits:	tca6424
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun	  40 bits:	pca9505, pca9698
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	  Now, max 24 bits chips and PCA953X compatible chips are
296*4882a593Smuzhiyun	  supported
297*4882a593Smuzhiyun
298*4882a593Smuzhiyunconfig MPC85XX_GPIO
299*4882a593Smuzhiyun	bool "Freescale MPC85XX GPIO driver"
300*4882a593Smuzhiyun	depends on DM_GPIO
301*4882a593Smuzhiyun	help
302*4882a593Smuzhiyun	  This driver supports the built-in GPIO controller of MPC85XX CPUs.
303*4882a593Smuzhiyun	  Each GPIO bank is identified by its own entry in the device tree,
304*4882a593Smuzhiyun	  i.e.
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun	  gpio-controller@fc00 {
307*4882a593Smuzhiyun		#gpio-cells = <2>;
308*4882a593Smuzhiyun		compatible = "fsl,pq3-gpio";
309*4882a593Smuzhiyun		reg = <0xfc00 0x100>
310*4882a593Smuzhiyun	  }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	  By default, each bank is assumed to have 32 GPIOs, but the ngpios
313*4882a593Smuzhiyun	  setting is honored, so the number of GPIOs for each bank is
314*4882a593Smuzhiyun	  configurable to match the actual GPIO count of the SoC (e.g. the
315*4882a593Smuzhiyun	  32/32/23 banks of the P1022 SoC).
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	  Aside from the standard functions of input/output mode, and output
318*4882a593Smuzhiyun	  value setting, the open-drain feature, which can configure individual
319*4882a593Smuzhiyun	  GPIOs to work as open-drain outputs, is supported.
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun	  The driver has been tested on MPC85XX, but it is likely that other
322*4882a593Smuzhiyun	  PowerQUICC III devices will work as well.
323*4882a593Smuzhiyunendmenu
324