1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 Altera Corporation <www.altera.com>
3*4882a593Smuzhiyun * All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: BSD-3-Clause
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <asm/arch/fpga_manager.h>
12*4882a593Smuzhiyun #include <asm/arch/reset_manager.h>
13*4882a593Smuzhiyun #include <asm/arch/system_manager.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* Timeout count */
18*4882a593Smuzhiyun #define FPGA_TIMEOUT_CNT 0x1000000
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct socfpga_fpga_manager *fpgamgr_regs =
21*4882a593Smuzhiyun (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
22*4882a593Smuzhiyun
fpgamgr_dclkcnt_set(unsigned long cnt)23*4882a593Smuzhiyun int fpgamgr_dclkcnt_set(unsigned long cnt)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun unsigned long i;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Clear any existing done status */
28*4882a593Smuzhiyun if (readl(&fpgamgr_regs->dclkstat))
29*4882a593Smuzhiyun writel(0x1, &fpgamgr_regs->dclkstat);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Write the dclkcnt */
32*4882a593Smuzhiyun writel(cnt, &fpgamgr_regs->dclkcnt);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Wait till the dclkcnt done */
35*4882a593Smuzhiyun for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
36*4882a593Smuzhiyun if (!readl(&fpgamgr_regs->dclkstat))
37*4882a593Smuzhiyun continue;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun writel(0x1, &fpgamgr_regs->dclkstat);
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return -ETIMEDOUT;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Write the RBF data to FPGA Manager */
fpgamgr_program_write(const void * rbf_data,size_t rbf_size)47*4882a593Smuzhiyun void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun uint32_t src = (uint32_t)rbf_data;
50*4882a593Smuzhiyun uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Number of loops for 32-byte long copying. */
53*4882a593Smuzhiyun uint32_t loops32 = rbf_size / 32;
54*4882a593Smuzhiyun /* Number of loops for 4-byte long copying + trailing bytes */
55*4882a593Smuzhiyun uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun asm volatile(
58*4882a593Smuzhiyun "1: ldmia %0!, {r0-r7}\n"
59*4882a593Smuzhiyun " stmia %1!, {r0-r7}\n"
60*4882a593Smuzhiyun " sub %1, #32\n"
61*4882a593Smuzhiyun " subs %2, #1\n"
62*4882a593Smuzhiyun " bne 1b\n"
63*4882a593Smuzhiyun " cmp %3, #0\n"
64*4882a593Smuzhiyun " beq 3f\n"
65*4882a593Smuzhiyun "2: ldr %2, [%0], #4\n"
66*4882a593Smuzhiyun " str %2, [%1]\n"
67*4882a593Smuzhiyun " subs %3, #1\n"
68*4882a593Smuzhiyun " bne 2b\n"
69*4882a593Smuzhiyun "3: nop\n"
70*4882a593Smuzhiyun : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
71*4882a593Smuzhiyun : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74