1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# (C) Copyright 2008 3*4882a593Smuzhiyun# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunobj-y += fpga.o 9*4882a593Smuzhiyunobj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o 10*4882a593Smuzhiyunobj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o 11*4882a593Smuzhiyunobj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o 12*4882a593Smuzhiyunobj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o 13*4882a593Smuzhiyunobj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o 14*4882a593Smuzhiyunobj-$(CONFIG_FPGA_XILINX) += xilinx.o 15*4882a593Smuzhiyunobj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o 16*4882a593Smuzhiyunifdef CONFIG_FPGA_ALTERA 17*4882a593Smuzhiyunobj-y += altera.o 18*4882a593Smuzhiyunobj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o 19*4882a593Smuzhiyunobj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o 20*4882a593Smuzhiyunobj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o 21*4882a593Smuzhiyunobj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o 22*4882a593Smuzhiyunobj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o 23*4882a593Smuzhiyunobj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o 24*4882a593Smuzhiyunobj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o 25*4882a593Smuzhiyunendif 26