1*4882a593Smuzhiyunmenu "DMA Support" 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig DMA 4*4882a593Smuzhiyun bool "Enable Driver Model for DMA drivers" 5*4882a593Smuzhiyun depends on DM 6*4882a593Smuzhiyun help 7*4882a593Smuzhiyun Enable driver model for DMA. DMA engines can do 8*4882a593Smuzhiyun asynchronous data transfers without involving the host 9*4882a593Smuzhiyun CPU. Currently, this framework can be used to offload 10*4882a593Smuzhiyun memory copies to and from devices like qspi, ethernet 11*4882a593Smuzhiyun etc Drivers provide methods to access the DMA devices 12*4882a593Smuzhiyun buses that is used to transfer data to and from memory. 13*4882a593Smuzhiyun The uclass interface is defined in include/dma.h. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig TI_EDMA3 16*4882a593Smuzhiyun bool "TI EDMA3 driver" 17*4882a593Smuzhiyun help 18*4882a593Smuzhiyun Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. 19*4882a593Smuzhiyun This driver support data transfer between memory 20*4882a593Smuzhiyun regions. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunconfig APBH_DMA 23*4882a593Smuzhiyun bool "Support APBH DMA" 24*4882a593Smuzhiyun depends on MX23 || MX28 || MX6 || MX7 25*4882a593Smuzhiyun help 26*4882a593Smuzhiyun Enable APBH DMA driver. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunif APBH_DMA 29*4882a593Smuzhiyunconfig APBH_DMA_BURST 30*4882a593Smuzhiyun bool "Enable DMA BURST" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunconfig APBH_DMA_BURST8 33*4882a593Smuzhiyun bool "Enable DMA BURST8" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunendif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunendmenu # menu "DMA Support" 38