1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MICROCHIP_DDR2_TIMING_H 9*4882a593Smuzhiyun #define __MICROCHIP_DDR2_TIMING_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* MPLL freq is 400MHz */ 12*4882a593Smuzhiyun #define T_CK 2500 /* 2500 psec */ 13*4882a593Smuzhiyun #define T_CK_CTRL (T_CK * 2) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Burst length in cycles */ 16*4882a593Smuzhiyun #define BL 2 17*4882a593Smuzhiyun /* default CAS latency for all speed grades */ 18*4882a593Smuzhiyun #define RL 5 19*4882a593Smuzhiyun /* default write latency for all speed grades = CL-1 */ 20*4882a593Smuzhiyun #define WL 4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* From Micron MT47H64M16HR-3 data sheet */ 23*4882a593Smuzhiyun #define T_RFC_MIN 127500 /* psec */ 24*4882a593Smuzhiyun #define T_WR 15000 /* psec */ 25*4882a593Smuzhiyun #define T_RP 12500 /* psec */ 26*4882a593Smuzhiyun #define T_RCD 12500 /* psec */ 27*4882a593Smuzhiyun #define T_RRD 7500 /* psec */ 28*4882a593Smuzhiyun /* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */ 29*4882a593Smuzhiyun #define T_RRD_TCK 2 30*4882a593Smuzhiyun #define T_WTR 7500 /* psec */ 31*4882a593Smuzhiyun /* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */ 32*4882a593Smuzhiyun #define T_WTR_TCK 2 33*4882a593Smuzhiyun #define T_RTP 7500 /* psec */ 34*4882a593Smuzhiyun #define T_RTP_TCK (BL / 2) 35*4882a593Smuzhiyun #define T_XP_TCK 2 /* clocks */ 36*4882a593Smuzhiyun #define T_CKE_TCK 3 /* clocks */ 37*4882a593Smuzhiyun #define T_XSNR (T_RFC_MIN + 10000) /* psec */ 38*4882a593Smuzhiyun #define T_DLLK 200 /* clocks */ 39*4882a593Smuzhiyun #define T_RAS_MIN 45000 /* psec */ 40*4882a593Smuzhiyun #define T_RC 57500 /* psec */ 41*4882a593Smuzhiyun #define T_FAW 35000 /* psec */ 42*4882a593Smuzhiyun #define T_MRD_TCK 2 /* clocks */ 43*4882a593Smuzhiyun #define T_RFI 7800000 /* psec */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* DDR Addressing */ 46*4882a593Smuzhiyun #define COL_BITS 10 47*4882a593Smuzhiyun #define BA_BITS 3 48*4882a593Smuzhiyun #define ROW_BITS 13 49*4882a593Smuzhiyun #define CS_BITS 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* DDR Addressing scheme: {CS, ROW, BA, COL} */ 52*4882a593Smuzhiyun #define COL_HI_RSHFT 0 53*4882a593Smuzhiyun #define COL_HI_MASK 0 54*4882a593Smuzhiyun #define COL_LO_MASK ((1 << COL_BITS) - 1) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define BA_RSHFT COL_BITS 57*4882a593Smuzhiyun #define BA_MASK ((1 << BA_BITS) - 1) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) 60*4882a593Smuzhiyun #define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CS_ADDR_RSHIFT 0 63*4882a593Smuzhiyun #define CS_ADDR_MASK 0 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __MICROCHIP_DDR2_TIMING_H */ 66