1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MICROCHIP_DDR2_REGS_H 9*4882a593Smuzhiyun #define __MICROCHIP_DDR2_REGS_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bitops.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* DDR2 Controller */ 14*4882a593Smuzhiyun struct ddr2_ctrl_regs { 15*4882a593Smuzhiyun u32 tsel; 16*4882a593Smuzhiyun u32 minlim; 17*4882a593Smuzhiyun u32 reqprd; 18*4882a593Smuzhiyun u32 mincmd; 19*4882a593Smuzhiyun u32 memcon; 20*4882a593Smuzhiyun u32 memcfg0; 21*4882a593Smuzhiyun u32 memcfg1; 22*4882a593Smuzhiyun u32 memcfg2; 23*4882a593Smuzhiyun u32 memcfg3; 24*4882a593Smuzhiyun u32 memcfg4; 25*4882a593Smuzhiyun u32 refcfg; 26*4882a593Smuzhiyun u32 pwrcfg; 27*4882a593Smuzhiyun u32 dlycfg0; 28*4882a593Smuzhiyun u32 dlycfg1; 29*4882a593Smuzhiyun u32 dlycfg2; 30*4882a593Smuzhiyun u32 dlycfg3; 31*4882a593Smuzhiyun u32 odtcfg; 32*4882a593Smuzhiyun u32 xfercfg; 33*4882a593Smuzhiyun u32 cmdissue; 34*4882a593Smuzhiyun u32 odtencfg; 35*4882a593Smuzhiyun u32 memwidth; 36*4882a593Smuzhiyun u32 unused[11]; 37*4882a593Smuzhiyun u32 cmd10[16]; 38*4882a593Smuzhiyun u32 cmd20[16]; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Arbiter Config */ 42*4882a593Smuzhiyun #define MIN_LIM_WIDTH 5 43*4882a593Smuzhiyun #define RQST_PERIOD_WIDTH 8 44*4882a593Smuzhiyun #define MIN_CMDACPT_WIDTH 8 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Refresh Config */ 47*4882a593Smuzhiyun #define REFCNT_CLK(x) (x) 48*4882a593Smuzhiyun #define REFDLY_CLK(x) ((x) << 16) 49*4882a593Smuzhiyun #define MAX_PEND_REF(x) ((x) << 24) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Power Config */ 52*4882a593Smuzhiyun #define PRECH_PWR_DN_ONLY(x) ((x) << 22) 53*4882a593Smuzhiyun #define SELF_REF_DLY(x) ((x) << 12) 54*4882a593Smuzhiyun #define PWR_DN_DLY(x) ((x) << 4) 55*4882a593Smuzhiyun #define EN_AUTO_SELF_REF(x) ((x) << 3) 56*4882a593Smuzhiyun #define EN_AUTO_PWR_DN(x) ((x) << 2) 57*4882a593Smuzhiyun #define ERR_CORR_EN(x) ((x) << 1) 58*4882a593Smuzhiyun #define ECC_EN(x) (x) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Memory Width */ 61*4882a593Smuzhiyun #define HALF_RATE_MODE BIT(3) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Delay Config */ 64*4882a593Smuzhiyun #define ODTWLEN(x) ((x) << 20) 65*4882a593Smuzhiyun #define ODTRLEN(x) ((x) << 16) 66*4882a593Smuzhiyun #define ODTWDLY(x) ((x) << 12) 67*4882a593Smuzhiyun #define ODTRDLY(x) ((x) << 8) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Xfer Config */ 70*4882a593Smuzhiyun #define BIG_ENDIAN(x) ((x) << 31) 71*4882a593Smuzhiyun #define MAX_BURST(x) ((x) << 24) 72*4882a593Smuzhiyun #define RDATENDLY(x) ((x) << 16) 73*4882a593Smuzhiyun #define NXDATAVDLY(x) ((x) << 4) 74*4882a593Smuzhiyun #define NXTDATRQDLY(x) ((x) << 0) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Host Commands */ 77*4882a593Smuzhiyun #define IDLE_NOP 0x00ffffff 78*4882a593Smuzhiyun #define PRECH_ALL_CMD 0x00fff401 79*4882a593Smuzhiyun #define REF_CMD 0x00fff801 80*4882a593Smuzhiyun #define LOAD_MODE_CMD 0x00fff001 81*4882a593Smuzhiyun #define CKE_LOW 0x00ffeffe 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define NUM_HOST_CMDS 12 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Host CMD Issue */ 86*4882a593Smuzhiyun #define CMD_VALID BIT(4) 87*4882a593Smuzhiyun #define NUMHOSTCMD(x) (x) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Memory Control */ 90*4882a593Smuzhiyun #define INIT_DONE BIT(1) 91*4882a593Smuzhiyun #define INIT_START BIT(0) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Address Control */ 94*4882a593Smuzhiyun #define EN_AUTO_PRECH 0 95*4882a593Smuzhiyun #define SB_PRI 1 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* DDR2 Phy Register */ 98*4882a593Smuzhiyun struct ddr2_phy_regs { 99*4882a593Smuzhiyun u32 scl_start; 100*4882a593Smuzhiyun u32 unused1[2]; 101*4882a593Smuzhiyun u32 scl_latency; 102*4882a593Smuzhiyun u32 unused2[2]; 103*4882a593Smuzhiyun u32 scl_config_1; 104*4882a593Smuzhiyun u32 scl_config_2; 105*4882a593Smuzhiyun u32 pad_ctrl; 106*4882a593Smuzhiyun u32 dll_recalib; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* PHY PAD CONTROL */ 110*4882a593Smuzhiyun #define ODT_SEL BIT(0) 111*4882a593Smuzhiyun #define ODT_EN BIT(1) 112*4882a593Smuzhiyun #define DRIVE_SEL(x) ((x) << 2) 113*4882a593Smuzhiyun #define ODT_PULLDOWN(x) ((x) << 4) 114*4882a593Smuzhiyun #define ODT_PULLUP(x) ((x) << 6) 115*4882a593Smuzhiyun #define EXTRA_OEN_CLK(x) ((x) << 8) 116*4882a593Smuzhiyun #define NOEXT_DLL BIT(9) 117*4882a593Smuzhiyun #define DLR_DFT_WRCMD BIT(13) 118*4882a593Smuzhiyun #define HALF_RATE BIT(14) 119*4882a593Smuzhiyun #define DRVSTR_PFET(x) ((x) << 16) 120*4882a593Smuzhiyun #define DRVSTR_NFET(x) ((x) << 20) 121*4882a593Smuzhiyun #define RCVR_EN BIT(28) 122*4882a593Smuzhiyun #define PREAMBLE_DLY(x) ((x) << 29) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* PHY DLL RECALIBRATE */ 125*4882a593Smuzhiyun #define RECALIB_CNT(x) ((x) << 8) 126*4882a593Smuzhiyun #define DISABLE_RECALIB(x) ((x) << 26) 127*4882a593Smuzhiyun #define DELAY_START_VAL(x) ((x) << 28) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* PHY SCL CONFIG1 */ 130*4882a593Smuzhiyun #define SCL_BURST8 BIT(0) 131*4882a593Smuzhiyun #define SCL_DDR_CONNECTED BIT(1) 132*4882a593Smuzhiyun #define SCL_RCAS_LAT(x) ((x) << 4) 133*4882a593Smuzhiyun #define SCL_ODTCSWW BIT(24) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* PHY SCL CONFIG2 */ 136*4882a593Smuzhiyun #define SCL_CSEN BIT(0) 137*4882a593Smuzhiyun #define SCL_WCAS_LAT(x) ((x) << 8) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* PHY SCL Latency */ 140*4882a593Smuzhiyun #define SCL_CAPCLKDLY(x) ((x) << 0) 141*4882a593Smuzhiyun #define SCL_DDRCLKDLY(x) ((x) << 4) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* PHY SCL START */ 144*4882a593Smuzhiyun #define SCL_START BIT(28) 145*4882a593Smuzhiyun #define SCL_EN BIT(26) 146*4882a593Smuzhiyun #define SCL_LUBPASS (BIT(1) | BIT(0)) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #endif /* __MICROCHIP_DDR2_REGS_H */ 149