1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __XOR_REGS_H 8*4882a593Smuzhiyun #define __XOR_REGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * For controllers that have two XOR units, then chans 2 & 3 will be mapped 12*4882a593Smuzhiyun * to channels 0 & 1 of unit 1 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define XOR_UNIT(chan) ((chan) >> 1) 15*4882a593Smuzhiyun #define XOR_CHAN(chan) ((chan) & 1) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MV_XOR_REGS_OFFSET(unit) (0x60900) 18*4882a593Smuzhiyun #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* XOR Engine Control Register Map */ 21*4882a593Smuzhiyun #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) 22*4882a593Smuzhiyun #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) 23*4882a593Smuzhiyun #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* XOR Engine Interrupt Register Map */ 26*4882a593Smuzhiyun #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) 27*4882a593Smuzhiyun #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) 28*4882a593Smuzhiyun #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) 29*4882a593Smuzhiyun #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* XOR Engine Descriptor Register Map */ 32*4882a593Smuzhiyun #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) 33*4882a593Smuzhiyun #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) 34*4882a593Smuzhiyun #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) 37*4882a593Smuzhiyun #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) 38*4882a593Smuzhiyun #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0) 39*4882a593Smuzhiyun #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4) 40*4882a593Smuzhiyun #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8) 41*4882a593Smuzhiyun #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0) 42*4882a593Smuzhiyun #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* XOR register fileds */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* XOR Engine [0..1] Configuration Registers (XExCR) */ 47*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_OFFS (0) 48*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) 49*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) 50*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) 51*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) 52*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) 53*4882a593Smuzhiyun #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define XEXCR_SRC_BURST_LIMIT_OFFS (4) 56*4882a593Smuzhiyun #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) 57*4882a593Smuzhiyun #define XEXCR_DST_BURST_LIMIT_OFFS (8) 58*4882a593Smuzhiyun #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) 59*4882a593Smuzhiyun #define XEXCR_DRD_RES_SWP_OFFS (12) 60*4882a593Smuzhiyun #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) 61*4882a593Smuzhiyun #define XEXCR_DWR_REQ_SWP_OFFS (13) 62*4882a593Smuzhiyun #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) 63*4882a593Smuzhiyun #define XEXCR_DES_SWP_OFFS (14) 64*4882a593Smuzhiyun #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) 65*4882a593Smuzhiyun #define XEXCR_REG_ACC_PROTECT_OFFS (15) 66*4882a593Smuzhiyun #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* XOR Engine [0..1] Activation Registers (XExACTR) */ 69*4882a593Smuzhiyun #define XEXACTR_XESTART_OFFS (0) 70*4882a593Smuzhiyun #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) 71*4882a593Smuzhiyun #define XEXACTR_XESTOP_OFFS (1) 72*4882a593Smuzhiyun #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) 73*4882a593Smuzhiyun #define XEXACTR_XEPAUSE_OFFS (2) 74*4882a593Smuzhiyun #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) 75*4882a593Smuzhiyun #define XEXACTR_XERESTART_OFFS (3) 76*4882a593Smuzhiyun #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) 77*4882a593Smuzhiyun #define XEXACTR_XESTATUS_OFFS (4) 78*4882a593Smuzhiyun #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) 79*4882a593Smuzhiyun #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) 80*4882a593Smuzhiyun #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) 81*4882a593Smuzhiyun #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ 84*4882a593Smuzhiyun #define XEXDPR_DST_PTR_OFFS (0) 85*4882a593Smuzhiyun #define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS) 86*4882a593Smuzhiyun #define XEXDPR_DST_PTR_XOR_MASK (0x3F) 87*4882a593Smuzhiyun #define XEXDPR_DST_PTR_DMA_MASK (0x1F) 88*4882a593Smuzhiyun #define XEXDPR_DST_PTR_CRC_MASK (0x1F) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* XOR Engine[0..1] Block Size Registers (XExBSR) */ 91*4882a593Smuzhiyun #define XEXBSR_BLOCK_SIZE_OFFS (0) 92*4882a593Smuzhiyun #define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS) 93*4882a593Smuzhiyun #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) 94*4882a593Smuzhiyun #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* XOR Engine Address Decoding Register Map */ 97*4882a593Smuzhiyun #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) 98*4882a593Smuzhiyun #define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4))) 99*4882a593Smuzhiyun #define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4))) 100*4882a593Smuzhiyun #define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4))) 101*4882a593Smuzhiyun #define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4))) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __XOR_REGS_H */ 104