1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR3_AXP_CONFIG_H 8*4882a593Smuzhiyun #define __DDR3_AXP_CONFIG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * DDR3_LOG_LEVEL Information 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Level 0: Provides an error code in a case of failure, RL, WL errors 14*4882a593Smuzhiyun * and other algorithm failure 15*4882a593Smuzhiyun * Level 1: Provides the D-Unit setup (SPD/Static configuration) 16*4882a593Smuzhiyun * Level 2: Provides the windows margin as a results of DQS centeralization 17*4882a593Smuzhiyun * Level 3: Provides the windows margin of each DQ as a results of DQS 18*4882a593Smuzhiyun * centeralization 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #ifdef CONFIG_DDR_LOG_LEVEL 21*4882a593Smuzhiyun #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL 22*4882a593Smuzhiyun #else 23*4882a593Smuzhiyun #define DDR3_LOG_LEVEL 0 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DDR3_PBS 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* This flag allows the execution of SW WL/RL upon HW failure */ 29*4882a593Smuzhiyun #define DDR3_RUN_SW_WHEN_HW_FAIL 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * General Configurations 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * The following parameters are required for proper setup: 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * DDR_TARGET_FABRIC - Set desired fabric configuration 37*4882a593Smuzhiyun * (for sample@Reset fabfreq parameter) 38*4882a593Smuzhiyun * DRAM_ECC - Set ECC support 1/0 39*4882a593Smuzhiyun * BUS_WIDTH - 64/32 bit 40*4882a593Smuzhiyun * CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values 41*4882a593Smuzhiyun * DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board 42*4882a593Smuzhiyun * MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers 43*4882a593Smuzhiyun * values are taken statically) 44*4882a593Smuzhiyun * DDR3_TRAINING_DEBUG - Debug prints of internal code 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define DDR_TARGET_FABRIC 5 47*4882a593Smuzhiyun /* Only enable ECC if the board selects it */ 48*4882a593Smuzhiyun #ifdef CONFIG_BOARD_ECC_SUPPORT 49*4882a593Smuzhiyun #define DRAM_ECC 1 50*4882a593Smuzhiyun #else 51*4882a593Smuzhiyun #define DRAM_ECC 0 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #ifdef CONFIG_DDR_32BIT 55*4882a593Smuzhiyun #define BUS_WIDTH 32 56*4882a593Smuzhiyun #else 57*4882a593Smuzhiyun #define BUS_WIDTH 64 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #undef DQS_CLK_ALIGNED 61*4882a593Smuzhiyun #undef MIXED_DIMM_STATIC 62*4882a593Smuzhiyun #define DDR3_TRAINING_DEBUG 0 63*4882a593Smuzhiyun #define REG_DIMM_SKIP_WL 0 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Marvell boards specific configurations */ 66*4882a593Smuzhiyun #if defined(DB_78X60_PCAC) 67*4882a593Smuzhiyun #undef CONFIG_SPD_EEPROM 68*4882a593Smuzhiyun #define STATIC_TRAINING 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #if defined(DB_78X60_AMC) 72*4882a593Smuzhiyun #undef CONFIG_SPD_EEPROM 73*4882a593Smuzhiyun #undef DRAM_ECC 74*4882a593Smuzhiyun #define DRAM_ECC 1 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #ifdef CONFIG_SPD_EEPROM 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * DIMM support parameters: 80*4882a593Smuzhiyun * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T 81*4882a593Smuzhiyun * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs 82*4882a593Smuzhiyun * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...) 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define DRAM_2T 0x0 85*4882a593Smuzhiyun #define DIMM_CS_BITMAP 0xF 86*4882a593Smuzhiyun #define DUNIT_SPD 87*4882a593Smuzhiyun #endif 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #ifdef DRAM_ECC 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * ECC support parameters: 92*4882a593Smuzhiyun * 93*4882a593Smuzhiyun * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need 94*4882a593Smuzhiyun * to configure the scrubbing area 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define TRAINING_SIZE 0x20000 97*4882a593Smuzhiyun #define U_BOOT_START_ADDR 0 98*4882a593Smuzhiyun #define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */ 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * Registered DIMM Support - In case registered DIMM is attached, 103*4882a593Smuzhiyun * please supply the following values: 104*4882a593Smuzhiyun * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock 105*4882a593Smuzhiyun * Driver with Parity and Quad Chip 106*4882a593Smuzhiyun * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications") 107*4882a593Smuzhiyun * RC0: Global Features Control Word 108*4882a593Smuzhiyun * RC1: Clock Driver Enable Control Word 109*4882a593Smuzhiyun * RC2: Timing Control Word 110*4882a593Smuzhiyun * RC3-RC5 - taken from SPD 111*4882a593Smuzhiyun * RC8: Additional IBT Setting Control Word 112*4882a593Smuzhiyun * RC9: Power Saving Settings Control Word 113*4882a593Smuzhiyun * RC10: Encoding for RDIMM Operating Speed 114*4882a593Smuzhiyun * RC11: Operating Voltage VDD and VREFCA Control Word 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun #define RDIMM_RC0 0 117*4882a593Smuzhiyun #define RDIMM_RC1 0 118*4882a593Smuzhiyun #define RDIMM_RC2 0 119*4882a593Smuzhiyun #define RDIMM_RC8 0 120*4882a593Smuzhiyun #define RDIMM_RC9 0 121*4882a593Smuzhiyun #define RDIMM_RC10 0x2 122*4882a593Smuzhiyun #define RDIMM_RC11 0x0 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM) 125*4882a593Smuzhiyun #define DUNIT_STATIC 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM) 129*4882a593Smuzhiyun /* 130*4882a593Smuzhiyun * This flag allows the user to change the dram refresh cycle in ps, 131*4882a593Smuzhiyun * only in case of SPD or MIX DIMM topology 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #define TREFI_USER_EN 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #ifdef TREFI_USER_EN 136*4882a593Smuzhiyun #define TREFI_USER 3900000 137*4882a593Smuzhiyun #endif 138*4882a593Smuzhiyun #endif 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #ifdef CONFIG_SPD_EEPROM 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards. 143*4882a593Smuzhiyun * Enables I2C auto detection different options 144*4882a593Smuzhiyun */ 145*4882a593Smuzhiyun #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \ 146*4882a593Smuzhiyun defined(CONFIG_DB_784MP_GP) 147*4882a593Smuzhiyun #define AUTO_DETECTION_SUPPORT 148*4882a593Smuzhiyun #endif 149*4882a593Smuzhiyun #endif 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif /* __DDR3_AXP_CONFIG_H */ 152