1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _XOR_H 8*4882a593Smuzhiyun #define _XOR_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define SRAM_BASE 0x40000000 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "ddr3_hws_hw_training_def.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ 15*4882a593Smuzhiyun #define MV_XOR_MAX_CHAN 4 /* total channels for all units */ 16*4882a593Smuzhiyun #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * This structure describes address space window. Window base can be 22*4882a593Smuzhiyun * 64 bit, window size up to 4GB 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun struct addr_win { 25*4882a593Smuzhiyun u32 base_low; /* 32bit base low */ 26*4882a593Smuzhiyun u32 base_high; /* 32bit base high */ 27*4882a593Smuzhiyun u32 size; /* 32bit size */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* This structure describes SoC units address decode window */ 31*4882a593Smuzhiyun struct unit_win_info { 32*4882a593Smuzhiyun struct addr_win addr_win; /* An address window */ 33*4882a593Smuzhiyun int enable; /* Address decode window is enabled/disabled */ 34*4882a593Smuzhiyun u8 attrib; /* chip select attributes */ 35*4882a593Smuzhiyun u8 target_id; /* Target Id of this MV_TARGET */ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * This enumerator describes the type of functionality the XOR channel 40*4882a593Smuzhiyun * can have while using the same data structures. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun enum xor_type { 43*4882a593Smuzhiyun MV_XOR, /* XOR channel functions as XOR accelerator */ 44*4882a593Smuzhiyun MV_DMA, /* XOR channel functions as IDMA channel */ 45*4882a593Smuzhiyun MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun enum mv_state { 49*4882a593Smuzhiyun MV_IDLE, 50*4882a593Smuzhiyun MV_ACTIVE, 51*4882a593Smuzhiyun MV_PAUSED, 52*4882a593Smuzhiyun MV_UNDEFINED_STATE 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * This enumerator describes the set of commands that can be applied on 57*4882a593Smuzhiyun * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 58*4882a593Smuzhiyun * status (see MV_STATE enumerator) 59*4882a593Smuzhiyun * 60*4882a593Smuzhiyun * Start can be applied only when status is IDLE 61*4882a593Smuzhiyun * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 62*4882a593Smuzhiyun * Pause can be applied only when status is ACTIVE 63*4882a593Smuzhiyun * Restart can be applied only when status is PAUSED 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun enum mv_command { 66*4882a593Smuzhiyun MV_START, /* Start */ 67*4882a593Smuzhiyun MV_STOP, /* Stop */ 68*4882a593Smuzhiyun MV_PAUSE, /* Pause */ 69*4882a593Smuzhiyun MV_RESTART /* Restart */ 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun enum xor_override_target { 73*4882a593Smuzhiyun SRC_ADDR0, /* Source Address #0 Control */ 74*4882a593Smuzhiyun SRC_ADDR1, /* Source Address #1 Control */ 75*4882a593Smuzhiyun SRC_ADDR2, /* Source Address #2 Control */ 76*4882a593Smuzhiyun SRC_ADDR3, /* Source Address #3 Control */ 77*4882a593Smuzhiyun SRC_ADDR4, /* Source Address #4 Control */ 78*4882a593Smuzhiyun SRC_ADDR5, /* Source Address #5 Control */ 79*4882a593Smuzhiyun SRC_ADDR6, /* Source Address #6 Control */ 80*4882a593Smuzhiyun SRC_ADDR7, /* Source Address #7 Control */ 81*4882a593Smuzhiyun XOR_DST_ADDR, /* Destination Address Control */ 82*4882a593Smuzhiyun XOR_NEXT_DESC /* Next Descriptor Address Control */ 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun enum mv_state mv_xor_state_get(u32 chan); 86*4882a593Smuzhiyun void mv_xor_hal_init(u32 xor_chan_num); 87*4882a593Smuzhiyun int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl); 88*4882a593Smuzhiyun int mv_xor_command_set(u32 chan, enum mv_command command); 89*4882a593Smuzhiyun int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num, 90*4882a593Smuzhiyun int enable); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif 93