xref: /OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/ddr3_topology_def.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) Marvell International Ltd. and its affiliates
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _DDR3_TOPOLOGY_DEF_H
8*4882a593Smuzhiyun #define _DDR3_TOPOLOGY_DEF_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* TOPOLOGY */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun enum hws_speed_bin {
13*4882a593Smuzhiyun 	SPEED_BIN_DDR_800D,
14*4882a593Smuzhiyun 	SPEED_BIN_DDR_800E,
15*4882a593Smuzhiyun 	SPEED_BIN_DDR_1066E,
16*4882a593Smuzhiyun 	SPEED_BIN_DDR_1066F,
17*4882a593Smuzhiyun 	SPEED_BIN_DDR_1066G,
18*4882a593Smuzhiyun 	SPEED_BIN_DDR_1333F,
19*4882a593Smuzhiyun 	SPEED_BIN_DDR_1333G,
20*4882a593Smuzhiyun 	SPEED_BIN_DDR_1333H,
21*4882a593Smuzhiyun 	SPEED_BIN_DDR_1333J,
22*4882a593Smuzhiyun 	SPEED_BIN_DDR_1600G,
23*4882a593Smuzhiyun 	SPEED_BIN_DDR_1600H,
24*4882a593Smuzhiyun 	SPEED_BIN_DDR_1600J,
25*4882a593Smuzhiyun 	SPEED_BIN_DDR_1600K,
26*4882a593Smuzhiyun 	SPEED_BIN_DDR_1866J,
27*4882a593Smuzhiyun 	SPEED_BIN_DDR_1866K,
28*4882a593Smuzhiyun 	SPEED_BIN_DDR_1866L,
29*4882a593Smuzhiyun 	SPEED_BIN_DDR_1866M,
30*4882a593Smuzhiyun 	SPEED_BIN_DDR_2133K,
31*4882a593Smuzhiyun 	SPEED_BIN_DDR_2133L,
32*4882a593Smuzhiyun 	SPEED_BIN_DDR_2133M,
33*4882a593Smuzhiyun 	SPEED_BIN_DDR_2133N,
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	SPEED_BIN_DDR_1333H_EXT,
36*4882a593Smuzhiyun 	SPEED_BIN_DDR_1600K_EXT,
37*4882a593Smuzhiyun 	SPEED_BIN_DDR_1866M_EXT
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun enum hws_ddr_freq {
41*4882a593Smuzhiyun 	DDR_FREQ_LOW_FREQ,
42*4882a593Smuzhiyun 	DDR_FREQ_400,
43*4882a593Smuzhiyun 	DDR_FREQ_533,
44*4882a593Smuzhiyun 	DDR_FREQ_667,
45*4882a593Smuzhiyun 	DDR_FREQ_800,
46*4882a593Smuzhiyun 	DDR_FREQ_933,
47*4882a593Smuzhiyun 	DDR_FREQ_1066,
48*4882a593Smuzhiyun 	DDR_FREQ_311,
49*4882a593Smuzhiyun 	DDR_FREQ_333,
50*4882a593Smuzhiyun 	DDR_FREQ_467,
51*4882a593Smuzhiyun 	DDR_FREQ_850,
52*4882a593Smuzhiyun 	DDR_FREQ_600,
53*4882a593Smuzhiyun 	DDR_FREQ_300,
54*4882a593Smuzhiyun 	DDR_FREQ_900,
55*4882a593Smuzhiyun 	DDR_FREQ_360,
56*4882a593Smuzhiyun 	DDR_FREQ_1000,
57*4882a593Smuzhiyun 	DDR_FREQ_LIMIT
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun enum speed_bin_table_elements {
61*4882a593Smuzhiyun 	SPEED_BIN_TRCD,
62*4882a593Smuzhiyun 	SPEED_BIN_TRP,
63*4882a593Smuzhiyun 	SPEED_BIN_TRAS,
64*4882a593Smuzhiyun 	SPEED_BIN_TRC,
65*4882a593Smuzhiyun 	SPEED_BIN_TRRD1K,
66*4882a593Smuzhiyun 	SPEED_BIN_TRRD2K,
67*4882a593Smuzhiyun 	SPEED_BIN_TPD,
68*4882a593Smuzhiyun 	SPEED_BIN_TFAW1K,
69*4882a593Smuzhiyun 	SPEED_BIN_TFAW2K,
70*4882a593Smuzhiyun 	SPEED_BIN_TWTR,
71*4882a593Smuzhiyun 	SPEED_BIN_TRTP,
72*4882a593Smuzhiyun 	SPEED_BIN_TWR,
73*4882a593Smuzhiyun 	SPEED_BIN_TMOD
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #endif /* _DDR3_TOPOLOGY_DEF_H */
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