1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DDR3_LOGGING_CONFIG_H 8*4882a593Smuzhiyun #define _DDR3_LOGGING_CONFIG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifdef SILENT_LIB 11*4882a593Smuzhiyun #define DEBUG_TRAINING_BIST_ENGINE(level, s) 12*4882a593Smuzhiyun #define DEBUG_TRAINING_IP(level, s) 13*4882a593Smuzhiyun #define DEBUG_CENTRALIZATION_ENGINE(level, s) 14*4882a593Smuzhiyun #define DEBUG_TRAINING_HW_ALG(level, s) 15*4882a593Smuzhiyun #define DEBUG_TRAINING_IP_ENGINE(level, s) 16*4882a593Smuzhiyun #define DEBUG_LEVELING(level, s) 17*4882a593Smuzhiyun #define DEBUG_PBS_ENGINE(level, s) 18*4882a593Smuzhiyun #define DEBUG_TRAINING_STATIC_IP(level, s) 19*4882a593Smuzhiyun #define DEBUG_TRAINING_ACCESS(level, s) 20*4882a593Smuzhiyun #else 21*4882a593Smuzhiyun #ifdef LIB_FUNCTIONAL_DEBUG_ONLY 22*4882a593Smuzhiyun #define DEBUG_TRAINING_BIST_ENGINE(level, s) 23*4882a593Smuzhiyun #define DEBUG_TRAINING_IP_ENGINE(level, s) 24*4882a593Smuzhiyun #define DEBUG_TRAINING_IP(level, s) \ 25*4882a593Smuzhiyun if (level >= debug_training) \ 26*4882a593Smuzhiyun printf s 27*4882a593Smuzhiyun #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 28*4882a593Smuzhiyun if (level >= debug_centralization) \ 29*4882a593Smuzhiyun printf s 30*4882a593Smuzhiyun #define DEBUG_TRAINING_HW_ALG(level, s) \ 31*4882a593Smuzhiyun if (level >= debug_training_hw_alg) \ 32*4882a593Smuzhiyun printf s 33*4882a593Smuzhiyun #define DEBUG_LEVELING(level, s) \ 34*4882a593Smuzhiyun if (level >= debug_leveling) \ 35*4882a593Smuzhiyun printf s 36*4882a593Smuzhiyun #define DEBUG_PBS_ENGINE(level, s) \ 37*4882a593Smuzhiyun if (level >= debug_pbs) \ 38*4882a593Smuzhiyun printf s 39*4882a593Smuzhiyun #define DEBUG_TRAINING_STATIC_IP(level, s) \ 40*4882a593Smuzhiyun if (level >= debug_training_static) \ 41*4882a593Smuzhiyun printf s 42*4882a593Smuzhiyun #define DEBUG_TRAINING_ACCESS(level, s) \ 43*4882a593Smuzhiyun if (level >= debug_training_access) \ 44*4882a593Smuzhiyun printf s 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun #define DEBUG_TRAINING_BIST_ENGINE(level, s) \ 47*4882a593Smuzhiyun if (level >= debug_training_bist) \ 48*4882a593Smuzhiyun printf s 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define DEBUG_TRAINING_IP_ENGINE(level, s) \ 51*4882a593Smuzhiyun if (level >= debug_training_ip) \ 52*4882a593Smuzhiyun printf s 53*4882a593Smuzhiyun #define DEBUG_TRAINING_IP(level, s) \ 54*4882a593Smuzhiyun if (level >= debug_training) \ 55*4882a593Smuzhiyun printf s 56*4882a593Smuzhiyun #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 57*4882a593Smuzhiyun if (level >= debug_centralization) \ 58*4882a593Smuzhiyun printf s 59*4882a593Smuzhiyun #define DEBUG_TRAINING_HW_ALG(level, s) \ 60*4882a593Smuzhiyun if (level >= debug_training_hw_alg) \ 61*4882a593Smuzhiyun printf s 62*4882a593Smuzhiyun #define DEBUG_LEVELING(level, s) \ 63*4882a593Smuzhiyun if (level >= debug_leveling) \ 64*4882a593Smuzhiyun printf s 65*4882a593Smuzhiyun #define DEBUG_PBS_ENGINE(level, s) \ 66*4882a593Smuzhiyun if (level >= debug_pbs) \ 67*4882a593Smuzhiyun printf s 68*4882a593Smuzhiyun #define DEBUG_TRAINING_STATIC_IP(level, s) \ 69*4882a593Smuzhiyun if (level >= debug_training_static) \ 70*4882a593Smuzhiyun printf s 71*4882a593Smuzhiyun #define DEBUG_TRAINING_ACCESS(level, s) \ 72*4882a593Smuzhiyun if (level >= debug_training_access) \ 73*4882a593Smuzhiyun printf s 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Logging defines */ 78*4882a593Smuzhiyun #define DEBUG_LEVEL_TRACE 1 79*4882a593Smuzhiyun #define DEBUG_LEVEL_INFO 2 80*4882a593Smuzhiyun #define DEBUG_LEVEL_ERROR 3 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun enum ddr_lib_debug_block { 83*4882a593Smuzhiyun DEBUG_BLOCK_STATIC, 84*4882a593Smuzhiyun DEBUG_BLOCK_TRAINING_MAIN, 85*4882a593Smuzhiyun DEBUG_BLOCK_LEVELING, 86*4882a593Smuzhiyun DEBUG_BLOCK_CENTRALIZATION, 87*4882a593Smuzhiyun DEBUG_BLOCK_PBS, 88*4882a593Smuzhiyun DEBUG_BLOCK_IP, 89*4882a593Smuzhiyun DEBUG_BLOCK_BIST, 90*4882a593Smuzhiyun DEBUG_BLOCK_ALG, 91*4882a593Smuzhiyun DEBUG_BLOCK_DEVICE, 92*4882a593Smuzhiyun DEBUG_BLOCK_ACCESS, 93*4882a593Smuzhiyun DEBUG_STAGES_REG_DUMP, 94*4882a593Smuzhiyun /* All excluding IP and REG_DUMP, should be enabled separatelly */ 95*4882a593Smuzhiyun DEBUG_BLOCK_ALL 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun int ddr3_tip_print_log(u32 dev_num, u32 mem_addr); 99*4882a593Smuzhiyun int ddr3_tip_print_stability_log(u32 dev_num); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* _DDR3_LOGGING_CONFIG_H */ 102