1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DDR3_A38X_TOPOLOGY_H 8*4882a593Smuzhiyun #define _DDR3_A38X_TOPOLOGY_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ddr_topology_def.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Bus mask variants */ 13*4882a593Smuzhiyun #define BUS_MASK_32BIT 0xf 14*4882a593Smuzhiyun #define BUS_MASK_32BIT_ECC 0x1f 15*4882a593Smuzhiyun #define BUS_MASK_16BIT 0x3 16*4882a593Smuzhiyun #define BUS_MASK_16BIT_ECC 0x13 17*4882a593Smuzhiyun #define BUS_MASK_16BIT_ECC_PUP3 0xb 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DYNAMIC_CS_SIZE_CONFIG 20*4882a593Smuzhiyun #define DISABLE_L2_FILTERING_DURING_DDR_TRAINING 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* _DDR3_A38X_TOPOLOGY_H */ 23