1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
12*4882a593Smuzhiyun #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
13*4882a593Smuzhiyun #endif
14*4882a593Smuzhiyun
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)15*4882a593Smuzhiyun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
16*4882a593Smuzhiyun unsigned int ctrl_num, int step)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun unsigned int i;
19*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun switch (ctrl_num) {
22*4882a593Smuzhiyun case 0:
23*4882a593Smuzhiyun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
24*4882a593Smuzhiyun break;
25*4882a593Smuzhiyun case 1:
26*4882a593Smuzhiyun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
27*4882a593Smuzhiyun break;
28*4882a593Smuzhiyun default:
29*4882a593Smuzhiyun printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
30*4882a593Smuzhiyun return;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
34*4882a593Smuzhiyun if (i == 0) {
35*4882a593Smuzhiyun out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
36*4882a593Smuzhiyun out_be32(&ddr->cs0_config, regs->cs[i].config);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun } else if (i == 1) {
39*4882a593Smuzhiyun out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
40*4882a593Smuzhiyun out_be32(&ddr->cs1_config, regs->cs[i].config);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun } else if (i == 2) {
43*4882a593Smuzhiyun out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
44*4882a593Smuzhiyun out_be32(&ddr->cs2_config, regs->cs[i].config);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun } else if (i == 3) {
47*4882a593Smuzhiyun out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
48*4882a593Smuzhiyun out_be32(&ddr->cs3_config, regs->cs[i].config);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
53*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
54*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
55*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
56*4882a593Smuzhiyun out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
57*4882a593Smuzhiyun out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
58*4882a593Smuzhiyun out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
59*4882a593Smuzhiyun out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
60*4882a593Smuzhiyun out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
61*4882a593Smuzhiyun out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
62*4882a593Smuzhiyun out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
63*4882a593Smuzhiyun out_be32(&ddr->init_addr, regs->ddr_init_addr);
64*4882a593Smuzhiyun out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun debug("before go\n");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * 200 painful micro-seconds must elapse between
70*4882a593Smuzhiyun * the DDR clock setup and the DDR config enable.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun udelay(200);
73*4882a593Smuzhiyun asm volatile("sync;isync");
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
81*4882a593Smuzhiyun udelay(10000); /* throttle polling rate */
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun }
84