1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <fsl_mmdc.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
set_wait_for_bits_clear(void * ptr,u32 value,u32 bits)15*4882a593Smuzhiyun static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun int timeout = 1000;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun out_be32(ptr, value);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun while (in_be32(ptr) & bits) {
22*4882a593Smuzhiyun udelay(100);
23*4882a593Smuzhiyun timeout--;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun if (timeout <= 0)
26*4882a593Smuzhiyun printf("Error: %p wait for clear timeout.\n", ptr);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
mmdc_init(const struct fsl_mmdc_info * priv)29*4882a593Smuzhiyun void mmdc_init(const struct fsl_mmdc_info *priv)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
32*4882a593Smuzhiyun unsigned int tmp;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* 1. set configuration request */
35*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* 2. configure the desired timing parameters */
38*4882a593Smuzhiyun out_be32(&mmdc->mdotc, priv->mdotc);
39*4882a593Smuzhiyun out_be32(&mmdc->mdcfg0, priv->mdcfg0);
40*4882a593Smuzhiyun out_be32(&mmdc->mdcfg1, priv->mdcfg1);
41*4882a593Smuzhiyun out_be32(&mmdc->mdcfg2, priv->mdcfg2);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* 3. configure DDR type and other miscellaneous parameters */
44*4882a593Smuzhiyun out_be32(&mmdc->mdmisc, priv->mdmisc);
45*4882a593Smuzhiyun out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
46*4882a593Smuzhiyun out_be32(&mmdc->mdrwd, priv->mdrwd);
47*4882a593Smuzhiyun out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* 4. configure the required delay while leaving reset */
50*4882a593Smuzhiyun out_be32(&mmdc->mdor, priv->mdor);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* 5. configure DDR physical parameters */
53*4882a593Smuzhiyun /* set row/column address width, burst length, data bus width */
54*4882a593Smuzhiyun tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
55*4882a593Smuzhiyun out_be32(&mmdc->mdctl, tmp);
56*4882a593Smuzhiyun /* configure address space partition */
57*4882a593Smuzhiyun out_be32(&mmdc->mdasp, priv->mdasp);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* 6. perform a ZQ calibration - not needed here, doing in #8b */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* 7. enable MMDC with the desired chip select */
62*4882a593Smuzhiyun #if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
63*4882a593Smuzhiyun out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
64*4882a593Smuzhiyun #elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
65*4882a593Smuzhiyun out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
69*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
70*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
73*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
76*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
79*4882a593Smuzhiyun CMD_ADDR_LSB_MR_ADDR(0x30) |
80*4882a593Smuzhiyun MDSCR_ENABLE_CON_REQ |
81*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* 8b. ZQ calibration */
84*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
85*4882a593Smuzhiyun CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
88*4882a593Smuzhiyun MPZQHWCTRL_ZQ_HW_FORCE);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* 9a. calibrations now, wr lvl */
91*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
92*4882a593Smuzhiyun MDSCR_ENABLE_CON_REQ |
93*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
96*4882a593Smuzhiyun CMD_NORMAL);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
99*4882a593Smuzhiyun MPWLGCR_HW_WL_EN);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun mdelay(1);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
104*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
105*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun mdelay(1);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* 9b. read DQS gating calibration */
110*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
111*4882a593Smuzhiyun CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
114*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* set absolute read delay offset */
119*4882a593Smuzhiyun if (priv->mprddlctl)
120*4882a593Smuzhiyun out_be32(&mmdc->mprddlctl, priv->mprddlctl);
121*4882a593Smuzhiyun else
122*4882a593Smuzhiyun out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun set_wait_for_bits_clear(&mmdc->mpdgctrl0,
125*4882a593Smuzhiyun AUTO_RD_DQS_GATING_CALIBRATION_EN,
126*4882a593Smuzhiyun AUTO_RD_DQS_GATING_CALIBRATION_EN);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
129*4882a593Smuzhiyun CMD_BANK_ADDR_3);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* 9c. read calibration */
132*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
133*4882a593Smuzhiyun CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
134*4882a593Smuzhiyun out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
135*4882a593Smuzhiyun CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
136*4882a593Smuzhiyun out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
137*4882a593Smuzhiyun set_wait_for_bits_clear(&mmdc->mprddlhwctl,
138*4882a593Smuzhiyun MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
139*4882a593Smuzhiyun MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
142*4882a593Smuzhiyun CMD_BANK_ADDR_3);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* 10. configure power-down, self-refresh entry, exit parameters */
145*4882a593Smuzhiyun out_be32(&mmdc->mdpdc, priv->mdpdc);
146*4882a593Smuzhiyun out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* 11. ZQ config again? do nothing here */
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* 12. refresh scheme */
151*4882a593Smuzhiyun set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
152*4882a593Smuzhiyun MDREF_START_REFRESH);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* 13. disable CON_REQ */
155*4882a593Smuzhiyun out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
156*4882a593Smuzhiyun }
157