1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13 #include <common.h>
14 #include <fsl_ddr_sdram.h>
15 #include <fsl_errata.h>
16 #include <fsl_ddr.h>
17 #include <fsl_immap.h>
18 #include <asm/io.h>
19 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
20 defined(CONFIG_ARM)
21 #include <asm/arch/clock.h>
22 #endif
23
24 /*
25 * Determine Rtt value.
26 *
27 * This should likely be either board or controller specific.
28 *
29 * Rtt(nominal) - DDR2:
30 * 0 = Rtt disabled
31 * 1 = 75 ohm
32 * 2 = 150 ohm
33 * 3 = 50 ohm
34 * Rtt(nominal) - DDR3:
35 * 0 = Rtt disabled
36 * 1 = 60 ohm
37 * 2 = 120 ohm
38 * 3 = 40 ohm
39 * 4 = 20 ohm
40 * 5 = 30 ohm
41 *
42 * FIXME: Apparently 8641 needs a value of 2
43 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
44 *
45 * FIXME: There was some effort down this line earlier:
46 *
47 * unsigned int i;
48 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
52 * rtt = 2;
53 * break;
54 * }
55 * }
56 */
fsl_ddr_get_rtt(void)57 static inline int fsl_ddr_get_rtt(void)
58 {
59 int rtt;
60
61 #if defined(CONFIG_SYS_FSL_DDR1)
62 rtt = 0;
63 #elif defined(CONFIG_SYS_FSL_DDR2)
64 rtt = 3;
65 #else
66 rtt = 0;
67 #endif
68
69 return rtt;
70 }
71
72 #ifdef CONFIG_SYS_FSL_DDR4
73 /*
74 * compute CAS write latency according to DDR4 spec
75 * CWL = 9 for <= 1600MT/s
76 * 10 for <= 1866MT/s
77 * 11 for <= 2133MT/s
78 * 12 for <= 2400MT/s
79 * 14 for <= 2667MT/s
80 * 16 for <= 2933MT/s
81 * 18 for higher
82 */
compute_cas_write_latency(const unsigned int ctrl_num)83 static inline unsigned int compute_cas_write_latency(
84 const unsigned int ctrl_num)
85 {
86 unsigned int cwl;
87 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
88 if (mclk_ps >= 1250)
89 cwl = 9;
90 else if (mclk_ps >= 1070)
91 cwl = 10;
92 else if (mclk_ps >= 935)
93 cwl = 11;
94 else if (mclk_ps >= 833)
95 cwl = 12;
96 else if (mclk_ps >= 750)
97 cwl = 14;
98 else if (mclk_ps >= 681)
99 cwl = 16;
100 else
101 cwl = 18;
102
103 return cwl;
104 }
105 #else
106 /*
107 * compute the CAS write latency according to DDR3 spec
108 * CWL = 5 if tCK >= 2.5ns
109 * 6 if 2.5ns > tCK >= 1.875ns
110 * 7 if 1.875ns > tCK >= 1.5ns
111 * 8 if 1.5ns > tCK >= 1.25ns
112 * 9 if 1.25ns > tCK >= 1.07ns
113 * 10 if 1.07ns > tCK >= 0.935ns
114 * 11 if 0.935ns > tCK >= 0.833ns
115 * 12 if 0.833ns > tCK >= 0.75ns
116 */
compute_cas_write_latency(const unsigned int ctrl_num)117 static inline unsigned int compute_cas_write_latency(
118 const unsigned int ctrl_num)
119 {
120 unsigned int cwl;
121 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
122
123 if (mclk_ps >= 2500)
124 cwl = 5;
125 else if (mclk_ps >= 1875)
126 cwl = 6;
127 else if (mclk_ps >= 1500)
128 cwl = 7;
129 else if (mclk_ps >= 1250)
130 cwl = 8;
131 else if (mclk_ps >= 1070)
132 cwl = 9;
133 else if (mclk_ps >= 935)
134 cwl = 10;
135 else if (mclk_ps >= 833)
136 cwl = 11;
137 else if (mclk_ps >= 750)
138 cwl = 12;
139 else {
140 cwl = 12;
141 printf("Warning: CWL is out of range\n");
142 }
143 return cwl;
144 }
145 #endif
146
147 /* Chip Select Configuration (CSn_CONFIG) */
set_csn_config(int dimm_number,int i,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const dimm_params_t * dimm_params)148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
149 const memctl_options_t *popts,
150 const dimm_params_t *dimm_params)
151 {
152 unsigned int cs_n_en = 0; /* Chip Select enable */
153 unsigned int intlv_en = 0; /* Memory controller interleave enable */
154 unsigned int intlv_ctl = 0; /* Interleaving control */
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
156 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
157 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
158 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
159 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
160 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
161 int go_config = 0;
162 #ifdef CONFIG_SYS_FSL_DDR4
163 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
164 #else
165 unsigned int n_banks_per_sdram_device;
166 #endif
167
168 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
169 switch (i) {
170 case 0:
171 if (dimm_params[dimm_number].n_ranks > 0) {
172 go_config = 1;
173 /* These fields only available in CS0_CONFIG */
174 if (!popts->memctl_interleaving)
175 break;
176 switch (popts->memctl_interleaving_mode) {
177 case FSL_DDR_256B_INTERLEAVING:
178 case FSL_DDR_CACHE_LINE_INTERLEAVING:
179 case FSL_DDR_PAGE_INTERLEAVING:
180 case FSL_DDR_BANK_INTERLEAVING:
181 case FSL_DDR_SUPERBANK_INTERLEAVING:
182 intlv_en = popts->memctl_interleaving;
183 intlv_ctl = popts->memctl_interleaving_mode;
184 break;
185 default:
186 break;
187 }
188 }
189 break;
190 case 1:
191 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
192 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
193 go_config = 1;
194 break;
195 case 2:
196 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
197 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
198 go_config = 1;
199 break;
200 case 3:
201 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
202 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
203 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
204 go_config = 1;
205 break;
206 default:
207 break;
208 }
209 if (go_config) {
210 cs_n_en = 1;
211 ap_n_en = popts->cs_local_opts[i].auto_precharge;
212 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
213 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
214 #ifdef CONFIG_SYS_FSL_DDR4
215 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
216 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
217 #else
218 n_banks_per_sdram_device
219 = dimm_params[dimm_number].n_banks_per_sdram_device;
220 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
221 #endif
222 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
223 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
224 }
225 ddr->cs[i].config = (0
226 | ((cs_n_en & 0x1) << 31)
227 | ((intlv_en & 0x3) << 29)
228 | ((intlv_ctl & 0xf) << 24)
229 | ((ap_n_en & 0x1) << 23)
230
231 /* XXX: some implementation only have 1 bit starting at left */
232 | ((odt_rd_cfg & 0x7) << 20)
233
234 /* XXX: Some implementation only have 1 bit starting at left */
235 | ((odt_wr_cfg & 0x7) << 16)
236
237 | ((ba_bits_cs_n & 0x3) << 14)
238 | ((row_bits_cs_n & 0x7) << 8)
239 #ifdef CONFIG_SYS_FSL_DDR4
240 | ((bg_bits_cs_n & 0x3) << 4)
241 #endif
242 | ((col_bits_cs_n & 0x7) << 0)
243 );
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
245 }
246
247 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
248 /* FIXME: 8572 */
set_csn_config_2(int i,fsl_ddr_cfg_regs_t * ddr)249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
250 {
251 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
252
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
255 }
256
257 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
258
259 #if !defined(CONFIG_SYS_FSL_DDR1)
260 /*
261 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
262 * Return 1 if other two slots configuration. Return 0 if single slot.
263 */
avoid_odt_overlap(const dimm_params_t * dimm_params)264 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
265 {
266 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
267 if (dimm_params[0].n_ranks == 4)
268 return 2;
269 #endif
270
271 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
272 if ((dimm_params[0].n_ranks == 2) &&
273 (dimm_params[1].n_ranks == 2))
274 return 2;
275
276 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
277 if (dimm_params[0].n_ranks == 4)
278 return 2;
279 #endif
280
281 if ((dimm_params[0].n_ranks != 0) &&
282 (dimm_params[2].n_ranks != 0))
283 return 1;
284 #endif
285 return 0;
286 }
287
288 /*
289 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
290 *
291 * Avoid writing for DDR I. The new PQ38 DDR controller
292 * dreams up non-zero default values to be backwards compatible.
293 */
set_timing_cfg_0(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const dimm_params_t * dimm_params)294 static void set_timing_cfg_0(const unsigned int ctrl_num,
295 fsl_ddr_cfg_regs_t *ddr,
296 const memctl_options_t *popts,
297 const dimm_params_t *dimm_params)
298 {
299 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
300 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
301 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
302 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
303 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
304
305 /* Active powerdown exit timing (tXARD and tXARDS). */
306 unsigned char act_pd_exit_mclk;
307 /* Precharge powerdown exit timing (tXP). */
308 unsigned char pre_pd_exit_mclk;
309 /* ODT powerdown exit timing (tAXPD). */
310 unsigned char taxpd_mclk = 0;
311 /* Mode register set cycle time (tMRD). */
312 unsigned char tmrd_mclk;
313 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
314 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
315 #endif
316
317 #ifdef CONFIG_SYS_FSL_DDR4
318 /* tXP=max(4nCK, 6ns) */
319 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
320 unsigned int data_rate = get_ddr_freq(ctrl_num);
321
322 /* for faster clock, need more time for data setup */
323 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
324
325 /*
326 * for single quad-rank DIMM and two-slot DIMMs
327 * to avoid ODT overlap
328 */
329 switch (avoid_odt_overlap(dimm_params)) {
330 case 2:
331 twrt_mclk = 2;
332 twwt_mclk = 2;
333 trrt_mclk = 2;
334 break;
335 default:
336 twrt_mclk = 1;
337 twwt_mclk = 1;
338 trrt_mclk = 0;
339 break;
340 }
341
342 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
343 pre_pd_exit_mclk = act_pd_exit_mclk;
344 /*
345 * MRS_CYC = max(tMRD, tMOD)
346 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
347 */
348 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
349 #elif defined(CONFIG_SYS_FSL_DDR3)
350 unsigned int data_rate = get_ddr_freq(ctrl_num);
351 int txp;
352 unsigned int ip_rev;
353 int odt_overlap;
354 /*
355 * (tXARD and tXARDS). Empirical?
356 * The DDR3 spec has not tXARD,
357 * we use the tXP instead of it.
358 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
359 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
360 * spec has not the tAXPD, we use
361 * tAXPD=1, need design to confirm.
362 */
363 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
364
365 ip_rev = fsl_ddr_get_version(ctrl_num);
366 if (ip_rev >= 0x40700) {
367 /*
368 * MRS_CYC = max(tMRD, tMOD)
369 * tMRD = 4nCK (8nCK for RDIMM)
370 * tMOD = max(12nCK, 15ns)
371 */
372 tmrd_mclk = max((unsigned int)12,
373 picos_to_mclk(ctrl_num, 15000));
374 } else {
375 /*
376 * MRS_CYC = tMRD
377 * tMRD = 4nCK (8nCK for RDIMM)
378 */
379 if (popts->registered_dimm_en)
380 tmrd_mclk = 8;
381 else
382 tmrd_mclk = 4;
383 }
384
385 /* set the turnaround time */
386
387 /*
388 * for single quad-rank DIMM and two-slot DIMMs
389 * to avoid ODT overlap
390 */
391 odt_overlap = avoid_odt_overlap(dimm_params);
392 switch (odt_overlap) {
393 case 2:
394 twwt_mclk = 2;
395 trrt_mclk = 1;
396 break;
397 case 1:
398 twwt_mclk = 1;
399 trrt_mclk = 0;
400 break;
401 default:
402 break;
403 }
404
405 /* for faster clock, need more time for data setup */
406 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
407
408 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
409 twrt_mclk = 1;
410
411 if (popts->dynamic_power == 0) { /* powerdown is not used */
412 act_pd_exit_mclk = 1;
413 pre_pd_exit_mclk = 1;
414 taxpd_mclk = 1;
415 } else {
416 /* act_pd_exit_mclk = tXARD, see above */
417 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
418 /* Mode register MR0[A12] is '1' - fast exit */
419 pre_pd_exit_mclk = act_pd_exit_mclk;
420 taxpd_mclk = 1;
421 }
422 #else /* CONFIG_SYS_FSL_DDR2 */
423 /*
424 * (tXARD and tXARDS). Empirical?
425 * tXARD = 2 for DDR2
426 * tXP=2
427 * tAXPD=8
428 */
429 act_pd_exit_mclk = 2;
430 pre_pd_exit_mclk = 2;
431 taxpd_mclk = 8;
432 tmrd_mclk = 2;
433 #endif
434
435 if (popts->trwt_override)
436 trwt_mclk = popts->trwt;
437
438 ddr->timing_cfg_0 = (0
439 | ((trwt_mclk & 0x3) << 30) /* RWT */
440 | ((twrt_mclk & 0x3) << 28) /* WRT */
441 | ((trrt_mclk & 0x3) << 26) /* RRT */
442 | ((twwt_mclk & 0x3) << 24) /* WWT */
443 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
444 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
445 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
446 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
447 );
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
449 }
450 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
451
452 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
set_timing_cfg_3(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency)453 static void set_timing_cfg_3(const unsigned int ctrl_num,
454 fsl_ddr_cfg_regs_t *ddr,
455 const memctl_options_t *popts,
456 const common_timing_params_t *common_dimm,
457 unsigned int cas_latency,
458 unsigned int additive_latency)
459 {
460 /* Extended precharge to activate interval (tRP) */
461 unsigned int ext_pretoact = 0;
462 /* Extended Activate to precharge interval (tRAS) */
463 unsigned int ext_acttopre = 0;
464 /* Extended activate to read/write interval (tRCD) */
465 unsigned int ext_acttorw = 0;
466 /* Extended refresh recovery time (tRFC) */
467 unsigned int ext_refrec;
468 /* Extended MCAS latency from READ cmd */
469 unsigned int ext_caslat = 0;
470 /* Extended additive latency */
471 unsigned int ext_add_lat = 0;
472 /* Extended last data to precharge interval (tWR) */
473 unsigned int ext_wrrec = 0;
474 /* Control Adjust */
475 unsigned int cntl_adj = 0;
476
477 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
478 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
479 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
480 ext_caslat = (2 * cas_latency - 1) >> 4;
481 ext_add_lat = additive_latency >> 4;
482 #ifdef CONFIG_SYS_FSL_DDR4
483 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
484 #else
485 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
486 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
487 #endif
488 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
489 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
490
491 ddr->timing_cfg_3 = (0
492 | ((ext_pretoact & 0x1) << 28)
493 | ((ext_acttopre & 0x3) << 24)
494 | ((ext_acttorw & 0x1) << 22)
495 | ((ext_refrec & 0x1F) << 16)
496 | ((ext_caslat & 0x3) << 12)
497 | ((ext_add_lat & 0x1) << 10)
498 | ((ext_wrrec & 0x1) << 8)
499 | ((cntl_adj & 0x7) << 0)
500 );
501 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
502 }
503
504 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
set_timing_cfg_1(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency)505 static void set_timing_cfg_1(const unsigned int ctrl_num,
506 fsl_ddr_cfg_regs_t *ddr,
507 const memctl_options_t *popts,
508 const common_timing_params_t *common_dimm,
509 unsigned int cas_latency)
510 {
511 /* Precharge-to-activate interval (tRP) */
512 unsigned char pretoact_mclk;
513 /* Activate to precharge interval (tRAS) */
514 unsigned char acttopre_mclk;
515 /* Activate to read/write interval (tRCD) */
516 unsigned char acttorw_mclk;
517 /* CASLAT */
518 unsigned char caslat_ctrl;
519 /* Refresh recovery time (tRFC) ; trfc_low */
520 unsigned char refrec_ctrl;
521 /* Last data to precharge minimum interval (tWR) */
522 unsigned char wrrec_mclk;
523 /* Activate-to-activate interval (tRRD) */
524 unsigned char acttoact_mclk;
525 /* Last write data pair to read command issue interval (tWTR) */
526 unsigned char wrtord_mclk;
527 #ifdef CONFIG_SYS_FSL_DDR4
528 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
529 static const u8 wrrec_table[] = {
530 10, 10, 10, 10, 10,
531 10, 10, 10, 10, 10,
532 12, 12, 14, 14, 16,
533 16, 18, 18, 20, 20,
534 24, 24, 24, 24};
535 #else
536 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
537 static const u8 wrrec_table[] = {
538 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
539 #endif
540
541 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
542 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
543 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
544
545 /*
546 * Translate CAS Latency to a DDR controller field value:
547 *
548 * CAS Lat DDR I DDR II Ctrl
549 * Clocks SPD Bit SPD Bit Value
550 * ------- ------- ------- -----
551 * 1.0 0 0001
552 * 1.5 1 0010
553 * 2.0 2 2 0011
554 * 2.5 3 0100
555 * 3.0 4 3 0101
556 * 3.5 5 0110
557 * 4.0 4 0111
558 * 4.5 1000
559 * 5.0 5 1001
560 */
561 #if defined(CONFIG_SYS_FSL_DDR1)
562 caslat_ctrl = (cas_latency + 1) & 0x07;
563 #elif defined(CONFIG_SYS_FSL_DDR2)
564 caslat_ctrl = 2 * cas_latency - 1;
565 #else
566 /*
567 * if the CAS latency more than 8 cycle,
568 * we need set extend bit for it at
569 * TIMING_CFG_3[EXT_CASLAT]
570 */
571 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
572 caslat_ctrl = 2 * cas_latency - 1;
573 else
574 caslat_ctrl = (cas_latency - 1) << 1;
575 #endif
576
577 #ifdef CONFIG_SYS_FSL_DDR4
578 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
579 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
580 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
581 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
582 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
583 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
584 else
585 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
586 #else
587 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
588 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
589 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
590 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
591 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
592 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
593 else
594 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
595 #endif
596 if (popts->otf_burst_chop_en)
597 wrrec_mclk += 2;
598
599 /*
600 * JEDEC has min requirement for tRRD
601 */
602 #if defined(CONFIG_SYS_FSL_DDR3)
603 if (acttoact_mclk < 4)
604 acttoact_mclk = 4;
605 #endif
606 /*
607 * JEDEC has some min requirements for tWTR
608 */
609 #if defined(CONFIG_SYS_FSL_DDR2)
610 if (wrtord_mclk < 2)
611 wrtord_mclk = 2;
612 #elif defined(CONFIG_SYS_FSL_DDR3)
613 if (wrtord_mclk < 4)
614 wrtord_mclk = 4;
615 #endif
616 if (popts->otf_burst_chop_en)
617 wrtord_mclk += 2;
618
619 ddr->timing_cfg_1 = (0
620 | ((pretoact_mclk & 0x0F) << 28)
621 | ((acttopre_mclk & 0x0F) << 24)
622 | ((acttorw_mclk & 0xF) << 20)
623 | ((caslat_ctrl & 0xF) << 16)
624 | ((refrec_ctrl & 0xF) << 12)
625 | ((wrrec_mclk & 0x0F) << 8)
626 | ((acttoact_mclk & 0x0F) << 4)
627 | ((wrtord_mclk & 0x0F) << 0)
628 );
629 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
630 }
631
632 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
set_timing_cfg_2(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency)633 static void set_timing_cfg_2(const unsigned int ctrl_num,
634 fsl_ddr_cfg_regs_t *ddr,
635 const memctl_options_t *popts,
636 const common_timing_params_t *common_dimm,
637 unsigned int cas_latency,
638 unsigned int additive_latency)
639 {
640 /* Additive latency */
641 unsigned char add_lat_mclk;
642 /* CAS-to-preamble override */
643 unsigned short cpo;
644 /* Write latency */
645 unsigned char wr_lat;
646 /* Read to precharge (tRTP) */
647 unsigned char rd_to_pre;
648 /* Write command to write data strobe timing adjustment */
649 unsigned char wr_data_delay;
650 /* Minimum CKE pulse width (tCKE) */
651 unsigned char cke_pls;
652 /* Window for four activates (tFAW) */
653 unsigned short four_act;
654 #ifdef CONFIG_SYS_FSL_DDR3
655 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
656 #endif
657
658 /* FIXME add check that this must be less than acttorw_mclk */
659 add_lat_mclk = additive_latency;
660 cpo = popts->cpo_override;
661
662 #if defined(CONFIG_SYS_FSL_DDR1)
663 /*
664 * This is a lie. It should really be 1, but if it is
665 * set to 1, bits overlap into the old controller's
666 * otherwise unused ACSM field. If we leave it 0, then
667 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
668 */
669 wr_lat = 0;
670 #elif defined(CONFIG_SYS_FSL_DDR2)
671 wr_lat = cas_latency - 1;
672 #else
673 wr_lat = compute_cas_write_latency(ctrl_num);
674 #endif
675
676 #ifdef CONFIG_SYS_FSL_DDR4
677 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
678 #else
679 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
680 #endif
681 /*
682 * JEDEC has some min requirements for tRTP
683 */
684 #if defined(CONFIG_SYS_FSL_DDR2)
685 if (rd_to_pre < 2)
686 rd_to_pre = 2;
687 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
688 if (rd_to_pre < 4)
689 rd_to_pre = 4;
690 #endif
691 if (popts->otf_burst_chop_en)
692 rd_to_pre += 2; /* according to UM */
693
694 wr_data_delay = popts->write_data_delay;
695 #ifdef CONFIG_SYS_FSL_DDR4
696 cpo = 0;
697 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
698 #elif defined(CONFIG_SYS_FSL_DDR3)
699 /*
700 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
701 * max(3nCK, 5.625ns) for DDR3-1066, 1333
702 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
703 */
704 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
705 (mclk_ps > 1245 ? 5625 : 5000)));
706 #else
707 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
708 #endif
709 four_act = picos_to_mclk(ctrl_num,
710 popts->tfaw_window_four_activates_ps);
711
712 ddr->timing_cfg_2 = (0
713 | ((add_lat_mclk & 0xf) << 28)
714 | ((cpo & 0x1f) << 23)
715 | ((wr_lat & 0xf) << 19)
716 | (((wr_lat & 0x10) >> 4) << 18)
717 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
718 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
719 | ((cke_pls & 0x7) << 6)
720 | ((four_act & 0x3f) << 0)
721 );
722 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
723 }
724
725 /* DDR SDRAM Register Control Word */
set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm)726 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
727 const memctl_options_t *popts,
728 const common_timing_params_t *common_dimm)
729 {
730 if (common_dimm->all_dimms_registered &&
731 !common_dimm->all_dimms_unbuffered) {
732 if (popts->rcw_override) {
733 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
734 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
735 } else {
736 ddr->ddr_sdram_rcw_1 =
737 common_dimm->rcw[0] << 28 | \
738 common_dimm->rcw[1] << 24 | \
739 common_dimm->rcw[2] << 20 | \
740 common_dimm->rcw[3] << 16 | \
741 common_dimm->rcw[4] << 12 | \
742 common_dimm->rcw[5] << 8 | \
743 common_dimm->rcw[6] << 4 | \
744 common_dimm->rcw[7];
745 ddr->ddr_sdram_rcw_2 =
746 common_dimm->rcw[8] << 28 | \
747 common_dimm->rcw[9] << 24 | \
748 common_dimm->rcw[10] << 20 | \
749 common_dimm->rcw[11] << 16 | \
750 common_dimm->rcw[12] << 12 | \
751 common_dimm->rcw[13] << 8 | \
752 common_dimm->rcw[14] << 4 | \
753 common_dimm->rcw[15];
754 }
755 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
756 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
757 }
758 }
759
760 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm)761 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
762 const memctl_options_t *popts,
763 const common_timing_params_t *common_dimm)
764 {
765 unsigned int mem_en; /* DDR SDRAM interface logic enable */
766 unsigned int sren; /* Self refresh enable (during sleep) */
767 unsigned int ecc_en; /* ECC enable. */
768 unsigned int rd_en; /* Registered DIMM enable */
769 unsigned int sdram_type; /* Type of SDRAM */
770 unsigned int dyn_pwr; /* Dynamic power management mode */
771 unsigned int dbw; /* DRAM dta bus width */
772 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
773 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
774 unsigned int threet_en; /* Enable 3T timing */
775 unsigned int twot_en; /* Enable 2T timing */
776 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
777 unsigned int x32_en = 0; /* x32 enable */
778 unsigned int pchb8 = 0; /* precharge bit 8 enable */
779 unsigned int hse; /* Global half strength override */
780 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
781 unsigned int mem_halt = 0; /* memory controller halt */
782 unsigned int bi = 0; /* Bypass initialization */
783
784 mem_en = 1;
785 sren = popts->self_refresh_in_sleep;
786 if (common_dimm->all_dimms_ecc_capable) {
787 /* Allow setting of ECC only if all DIMMs are ECC. */
788 ecc_en = popts->ecc_mode;
789 } else {
790 ecc_en = 0;
791 }
792
793 if (common_dimm->all_dimms_registered &&
794 !common_dimm->all_dimms_unbuffered) {
795 rd_en = 1;
796 twot_en = 0;
797 } else {
798 rd_en = 0;
799 twot_en = popts->twot_en;
800 }
801
802 sdram_type = CONFIG_FSL_SDRAM_TYPE;
803
804 dyn_pwr = popts->dynamic_power;
805 dbw = popts->data_bus_width;
806 /* 8-beat burst enable DDR-III case
807 * we must clear it when use the on-the-fly mode,
808 * must set it when use the 32-bits bus mode.
809 */
810 if ((sdram_type == SDRAM_TYPE_DDR3) ||
811 (sdram_type == SDRAM_TYPE_DDR4)) {
812 if (popts->burst_length == DDR_BL8)
813 eight_be = 1;
814 if (popts->burst_length == DDR_OTF)
815 eight_be = 0;
816 if (dbw == 0x1)
817 eight_be = 1;
818 }
819
820 threet_en = popts->threet_en;
821 ba_intlv_ctl = popts->ba_intlv_ctl;
822 hse = popts->half_strength_driver_enable;
823
824 /* set when ddr bus width < 64 */
825 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
826
827 ddr->ddr_sdram_cfg = (0
828 | ((mem_en & 0x1) << 31)
829 | ((sren & 0x1) << 30)
830 | ((ecc_en & 0x1) << 29)
831 | ((rd_en & 0x1) << 28)
832 | ((sdram_type & 0x7) << 24)
833 | ((dyn_pwr & 0x1) << 21)
834 | ((dbw & 0x3) << 19)
835 | ((eight_be & 0x1) << 18)
836 | ((ncap & 0x1) << 17)
837 | ((threet_en & 0x1) << 16)
838 | ((twot_en & 0x1) << 15)
839 | ((ba_intlv_ctl & 0x7F) << 8)
840 | ((x32_en & 0x1) << 5)
841 | ((pchb8 & 0x1) << 4)
842 | ((hse & 0x1) << 3)
843 | ((acc_ecc_en & 0x1) << 2)
844 | ((mem_halt & 0x1) << 1)
845 | ((bi & 0x1) << 0)
846 );
847 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
848 }
849
850 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
set_ddr_sdram_cfg_2(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const unsigned int unq_mrs_en)851 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
852 fsl_ddr_cfg_regs_t *ddr,
853 const memctl_options_t *popts,
854 const unsigned int unq_mrs_en)
855 {
856 unsigned int frc_sr = 0; /* Force self refresh */
857 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
858 unsigned int odt_cfg = 0; /* ODT configuration */
859 unsigned int num_pr; /* Number of posted refreshes */
860 unsigned int slow = 0; /* DDR will be run less than 1250 */
861 unsigned int x4_en = 0; /* x4 DRAM enable */
862 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
863 unsigned int ap_en; /* Address Parity Enable */
864 unsigned int d_init; /* DRAM data initialization */
865 unsigned int rcw_en = 0; /* Register Control Word Enable */
866 unsigned int md_en = 0; /* Mirrored DIMM Enable */
867 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
868 int i;
869 #ifndef CONFIG_SYS_FSL_DDR4
870 unsigned int dll_rst_dis = 1; /* DLL reset disable */
871 unsigned int dqs_cfg; /* DQS configuration */
872
873 dqs_cfg = popts->dqs_config;
874 #endif
875 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
876 if (popts->cs_local_opts[i].odt_rd_cfg
877 || popts->cs_local_opts[i].odt_wr_cfg) {
878 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
879 break;
880 }
881 }
882 sr_ie = popts->self_refresh_interrupt_en;
883 num_pr = 1; /* Make this configurable */
884
885 /*
886 * 8572 manual says
887 * {TIMING_CFG_1[PRETOACT]
888 * + [DDR_SDRAM_CFG_2[NUM_PR]
889 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
890 * << DDR_SDRAM_INTERVAL[REFINT]
891 */
892 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
893 obc_cfg = popts->otf_burst_chop_en;
894 #else
895 obc_cfg = 0;
896 #endif
897
898 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
899 slow = get_ddr_freq(ctrl_num) < 1249000000;
900 #endif
901
902 if (popts->registered_dimm_en)
903 rcw_en = 1;
904
905 /* DDR4 can have address parity for UDIMM and discrete */
906 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
907 (!popts->registered_dimm_en)) {
908 ap_en = 0;
909 } else {
910 ap_en = popts->ap_en;
911 }
912
913 x4_en = popts->x4_en ? 1 : 0;
914
915 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
916 /* Use the DDR controller to auto initialize memory. */
917 d_init = popts->ecc_init_using_memctl;
918 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
919 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
920 #else
921 /* Memory will be initialized via DMA, or not at all. */
922 d_init = 0;
923 #endif
924
925 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
926 md_en = popts->mirrored_dimm;
927 #endif
928 qd_en = popts->quad_rank_present ? 1 : 0;
929 ddr->ddr_sdram_cfg_2 = (0
930 | ((frc_sr & 0x1) << 31)
931 | ((sr_ie & 0x1) << 30)
932 #ifndef CONFIG_SYS_FSL_DDR4
933 | ((dll_rst_dis & 0x1) << 29)
934 | ((dqs_cfg & 0x3) << 26)
935 #endif
936 | ((odt_cfg & 0x3) << 21)
937 | ((num_pr & 0xf) << 12)
938 | ((slow & 1) << 11)
939 | (x4_en << 10)
940 | (qd_en << 9)
941 | (unq_mrs_en << 8)
942 | ((obc_cfg & 0x1) << 6)
943 | ((ap_en & 0x1) << 5)
944 | ((d_init & 0x1) << 4)
945 | ((rcw_en & 0x1) << 2)
946 | ((md_en & 0x1) << 0)
947 );
948 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
949 }
950
951 #ifdef CONFIG_SYS_FSL_DDR4
952 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
set_ddr_sdram_mode_2(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,const unsigned int unq_mrs_en)953 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
954 fsl_ddr_cfg_regs_t *ddr,
955 const memctl_options_t *popts,
956 const common_timing_params_t *common_dimm,
957 const unsigned int unq_mrs_en)
958 {
959 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
960 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
961 int i;
962 unsigned int wr_crc = 0; /* Disable */
963 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
964 unsigned int srt = 0; /* self-refresh temerature, normal range */
965 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
966 unsigned int mpr = 0; /* serial */
967 unsigned int wc_lat;
968 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
969
970 if (popts->rtt_override)
971 rtt_wr = popts->rtt_wr_override_value;
972 else
973 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
974
975 if (common_dimm->extended_op_srt)
976 srt = common_dimm->extended_op_srt;
977
978 esdmode2 = (0
979 | ((wr_crc & 0x1) << 12)
980 | ((rtt_wr & 0x3) << 9)
981 | ((srt & 0x3) << 6)
982 | ((cwl & 0x7) << 3));
983
984 if (mclk_ps >= 1250)
985 wc_lat = 0;
986 else if (mclk_ps >= 833)
987 wc_lat = 1;
988 else
989 wc_lat = 2;
990
991 esdmode3 = (0
992 | ((mpr & 0x3) << 11)
993 | ((wc_lat & 0x3) << 9));
994
995 ddr->ddr_sdram_mode_2 = (0
996 | ((esdmode2 & 0xFFFF) << 16)
997 | ((esdmode3 & 0xFFFF) << 0)
998 );
999 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1000
1001 if (unq_mrs_en) { /* unique mode registers are supported */
1002 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1003 if (popts->rtt_override)
1004 rtt_wr = popts->rtt_wr_override_value;
1005 else
1006 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1007
1008 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1009 esdmode2 |= (rtt_wr & 0x3) << 9;
1010 switch (i) {
1011 case 1:
1012 ddr->ddr_sdram_mode_4 = (0
1013 | ((esdmode2 & 0xFFFF) << 16)
1014 | ((esdmode3 & 0xFFFF) << 0)
1015 );
1016 break;
1017 case 2:
1018 ddr->ddr_sdram_mode_6 = (0
1019 | ((esdmode2 & 0xFFFF) << 16)
1020 | ((esdmode3 & 0xFFFF) << 0)
1021 );
1022 break;
1023 case 3:
1024 ddr->ddr_sdram_mode_8 = (0
1025 | ((esdmode2 & 0xFFFF) << 16)
1026 | ((esdmode3 & 0xFFFF) << 0)
1027 );
1028 break;
1029 }
1030 }
1031 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1032 ddr->ddr_sdram_mode_4);
1033 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1034 ddr->ddr_sdram_mode_6);
1035 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1036 ddr->ddr_sdram_mode_8);
1037 }
1038 }
1039 #elif defined(CONFIG_SYS_FSL_DDR3)
1040 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
set_ddr_sdram_mode_2(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,const unsigned int unq_mrs_en)1041 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1042 fsl_ddr_cfg_regs_t *ddr,
1043 const memctl_options_t *popts,
1044 const common_timing_params_t *common_dimm,
1045 const unsigned int unq_mrs_en)
1046 {
1047 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1048 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1049 int i;
1050 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1051 unsigned int srt = 0; /* self-refresh temerature, normal range */
1052 unsigned int asr = 0; /* auto self-refresh disable */
1053 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1054 unsigned int pasr = 0; /* partial array self refresh disable */
1055
1056 if (popts->rtt_override)
1057 rtt_wr = popts->rtt_wr_override_value;
1058 else
1059 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1060
1061 if (common_dimm->extended_op_srt)
1062 srt = common_dimm->extended_op_srt;
1063
1064 esdmode2 = (0
1065 | ((rtt_wr & 0x3) << 9)
1066 | ((srt & 0x1) << 7)
1067 | ((asr & 0x1) << 6)
1068 | ((cwl & 0x7) << 3)
1069 | ((pasr & 0x7) << 0));
1070 ddr->ddr_sdram_mode_2 = (0
1071 | ((esdmode2 & 0xFFFF) << 16)
1072 | ((esdmode3 & 0xFFFF) << 0)
1073 );
1074 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1075
1076 if (unq_mrs_en) { /* unique mode registers are supported */
1077 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1078 if (popts->rtt_override)
1079 rtt_wr = popts->rtt_wr_override_value;
1080 else
1081 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1082
1083 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1084 esdmode2 |= (rtt_wr & 0x3) << 9;
1085 switch (i) {
1086 case 1:
1087 ddr->ddr_sdram_mode_4 = (0
1088 | ((esdmode2 & 0xFFFF) << 16)
1089 | ((esdmode3 & 0xFFFF) << 0)
1090 );
1091 break;
1092 case 2:
1093 ddr->ddr_sdram_mode_6 = (0
1094 | ((esdmode2 & 0xFFFF) << 16)
1095 | ((esdmode3 & 0xFFFF) << 0)
1096 );
1097 break;
1098 case 3:
1099 ddr->ddr_sdram_mode_8 = (0
1100 | ((esdmode2 & 0xFFFF) << 16)
1101 | ((esdmode3 & 0xFFFF) << 0)
1102 );
1103 break;
1104 }
1105 }
1106 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1107 ddr->ddr_sdram_mode_4);
1108 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1109 ddr->ddr_sdram_mode_6);
1110 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1111 ddr->ddr_sdram_mode_8);
1112 }
1113 }
1114
1115 #else /* for DDR2 and DDR1 */
1116 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
set_ddr_sdram_mode_2(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,const unsigned int unq_mrs_en)1117 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1118 fsl_ddr_cfg_regs_t *ddr,
1119 const memctl_options_t *popts,
1120 const common_timing_params_t *common_dimm,
1121 const unsigned int unq_mrs_en)
1122 {
1123 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1124 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1125
1126 ddr->ddr_sdram_mode_2 = (0
1127 | ((esdmode2 & 0xFFFF) << 16)
1128 | ((esdmode3 & 0xFFFF) << 0)
1129 );
1130 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1131 }
1132 #endif
1133
1134 #ifdef CONFIG_SYS_FSL_DDR4
1135 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,const unsigned int unq_mrs_en)1136 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1137 const memctl_options_t *popts,
1138 const common_timing_params_t *common_dimm,
1139 const unsigned int unq_mrs_en)
1140 {
1141 int i;
1142 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1143 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1144 int rtt_park = 0;
1145 bool four_cs = false;
1146 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1147
1148 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1149 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1150 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1151 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1152 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1153 four_cs = true;
1154 #endif
1155 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1156 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
1157 rtt_park = four_cs ? 0 : 1;
1158 } else {
1159 esdmode5 = 0x00000400; /* Data mask enabled */
1160 }
1161
1162 /* set command/address parity latency */
1163 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1164 if (mclk_ps >= 935) {
1165 /* for DDR4-1600/1866/2133 */
1166 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1167 } else if (mclk_ps >= 833) {
1168 /* for DDR4-2400 */
1169 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1170 } else {
1171 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1172 }
1173 }
1174
1175 ddr->ddr_sdram_mode_9 = (0
1176 | ((esdmode4 & 0xffff) << 16)
1177 | ((esdmode5 & 0xffff) << 0)
1178 );
1179
1180 /* Normally only the first enabled CS use 0x500, others use 0x400
1181 * But when four chip-selects are all enabled, all mode registers
1182 * need 0x500 to park.
1183 */
1184
1185 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1186 if (unq_mrs_en) { /* unique mode registers are supported */
1187 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1188 if (!rtt_park &&
1189 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1190 esdmode5 |= 0x00000500; /* RTT_PARK */
1191 rtt_park = four_cs ? 0 : 1;
1192 } else {
1193 esdmode5 = 0x00000400;
1194 }
1195
1196 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1197 if (mclk_ps >= 935) {
1198 /* for DDR4-1600/1866/2133 */
1199 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1200 } else if (mclk_ps >= 833) {
1201 /* for DDR4-2400 */
1202 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1203 } else {
1204 printf("parity: mclk_ps = %d not supported\n",
1205 mclk_ps);
1206 }
1207 }
1208
1209 switch (i) {
1210 case 1:
1211 ddr->ddr_sdram_mode_11 = (0
1212 | ((esdmode4 & 0xFFFF) << 16)
1213 | ((esdmode5 & 0xFFFF) << 0)
1214 );
1215 break;
1216 case 2:
1217 ddr->ddr_sdram_mode_13 = (0
1218 | ((esdmode4 & 0xFFFF) << 16)
1219 | ((esdmode5 & 0xFFFF) << 0)
1220 );
1221 break;
1222 case 3:
1223 ddr->ddr_sdram_mode_15 = (0
1224 | ((esdmode4 & 0xFFFF) << 16)
1225 | ((esdmode5 & 0xFFFF) << 0)
1226 );
1227 break;
1228 }
1229 }
1230 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1231 ddr->ddr_sdram_mode_11);
1232 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1233 ddr->ddr_sdram_mode_13);
1234 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1235 ddr->ddr_sdram_mode_15);
1236 }
1237 }
1238
1239 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
set_ddr_sdram_mode_10(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,const unsigned int unq_mrs_en)1240 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1241 fsl_ddr_cfg_regs_t *ddr,
1242 const memctl_options_t *popts,
1243 const common_timing_params_t *common_dimm,
1244 const unsigned int unq_mrs_en)
1245 {
1246 int i;
1247 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1248 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1249 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1250
1251 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1252
1253 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1254 esdmode6 |= 1 << 6; /* Range 2 */
1255
1256 ddr->ddr_sdram_mode_10 = (0
1257 | ((esdmode6 & 0xffff) << 16)
1258 | ((esdmode7 & 0xffff) << 0)
1259 );
1260 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1261 if (unq_mrs_en) { /* unique mode registers are supported */
1262 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1263 switch (i) {
1264 case 1:
1265 ddr->ddr_sdram_mode_12 = (0
1266 | ((esdmode6 & 0xFFFF) << 16)
1267 | ((esdmode7 & 0xFFFF) << 0)
1268 );
1269 break;
1270 case 2:
1271 ddr->ddr_sdram_mode_14 = (0
1272 | ((esdmode6 & 0xFFFF) << 16)
1273 | ((esdmode7 & 0xFFFF) << 0)
1274 );
1275 break;
1276 case 3:
1277 ddr->ddr_sdram_mode_16 = (0
1278 | ((esdmode6 & 0xFFFF) << 16)
1279 | ((esdmode7 & 0xFFFF) << 0)
1280 );
1281 break;
1282 }
1283 }
1284 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1285 ddr->ddr_sdram_mode_12);
1286 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1287 ddr->ddr_sdram_mode_14);
1288 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1289 ddr->ddr_sdram_mode_16);
1290 }
1291 }
1292
1293 #endif
1294
1295 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
set_ddr_sdram_interval(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm)1296 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1297 fsl_ddr_cfg_regs_t *ddr,
1298 const memctl_options_t *popts,
1299 const common_timing_params_t *common_dimm)
1300 {
1301 unsigned int refint; /* Refresh interval */
1302 unsigned int bstopre; /* Precharge interval */
1303
1304 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1305
1306 bstopre = popts->bstopre;
1307
1308 /* refint field used 0x3FFF in earlier controllers */
1309 ddr->ddr_sdram_interval = (0
1310 | ((refint & 0xFFFF) << 16)
1311 | ((bstopre & 0x3FFF) << 0)
1312 );
1313 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1314 }
1315
1316 #ifdef CONFIG_SYS_FSL_DDR4
1317 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
set_ddr_sdram_mode(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency,const unsigned int unq_mrs_en)1318 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1319 fsl_ddr_cfg_regs_t *ddr,
1320 const memctl_options_t *popts,
1321 const common_timing_params_t *common_dimm,
1322 unsigned int cas_latency,
1323 unsigned int additive_latency,
1324 const unsigned int unq_mrs_en)
1325 {
1326 int i;
1327 unsigned short esdmode; /* Extended SDRAM mode */
1328 unsigned short sdmode; /* SDRAM mode */
1329
1330 /* Mode Register - MR1 */
1331 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1332 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1333 unsigned int rtt;
1334 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1335 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1336 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1337 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1338 0=Disable (Test/Debug) */
1339
1340 /* Mode Register - MR0 */
1341 unsigned int wr = 0; /* Write Recovery */
1342 unsigned int dll_rst; /* DLL Reset */
1343 unsigned int mode; /* Normal=0 or Test=1 */
1344 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1345 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1346 unsigned int bt;
1347 unsigned int bl; /* BL: Burst Length */
1348
1349 unsigned int wr_mclk;
1350 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1351 static const u8 wr_table[] = {
1352 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1353 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1354 static const u8 cas_latency_table[] = {
1355 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1356 9, 9, 10, 10, 11, 11};
1357
1358 if (popts->rtt_override)
1359 rtt = popts->rtt_override_value;
1360 else
1361 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1362
1363 if (additive_latency == (cas_latency - 1))
1364 al = 1;
1365 if (additive_latency == (cas_latency - 2))
1366 al = 2;
1367
1368 if (popts->quad_rank_present)
1369 dic = 1; /* output driver impedance 240/7 ohm */
1370
1371 /*
1372 * The esdmode value will also be used for writing
1373 * MR1 during write leveling for DDR3, although the
1374 * bits specifically related to the write leveling
1375 * scheme will be handled automatically by the DDR
1376 * controller. so we set the wrlvl_en = 0 here.
1377 */
1378 esdmode = (0
1379 | ((qoff & 0x1) << 12)
1380 | ((tdqs_en & 0x1) << 11)
1381 | ((rtt & 0x7) << 8)
1382 | ((wrlvl_en & 0x1) << 7)
1383 | ((al & 0x3) << 3)
1384 | ((dic & 0x3) << 1) /* DIC field is split */
1385 | ((dll_en & 0x1) << 0)
1386 );
1387
1388 /*
1389 * DLL control for precharge PD
1390 * 0=slow exit DLL off (tXPDLL)
1391 * 1=fast exit DLL on (tXP)
1392 */
1393
1394 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1395 if (wr_mclk <= 24) {
1396 wr = wr_table[wr_mclk - 10];
1397 } else {
1398 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1399 wr_mclk);
1400 }
1401
1402 dll_rst = 0; /* dll no reset */
1403 mode = 0; /* normal mode */
1404
1405 /* look up table to get the cas latency bits */
1406 if (cas_latency >= 9 && cas_latency <= 24)
1407 caslat = cas_latency_table[cas_latency - 9];
1408 else
1409 printf("Error: unsupported cas latency for mode register\n");
1410
1411 bt = 0; /* Nibble sequential */
1412
1413 switch (popts->burst_length) {
1414 case DDR_BL8:
1415 bl = 0;
1416 break;
1417 case DDR_OTF:
1418 bl = 1;
1419 break;
1420 case DDR_BC4:
1421 bl = 2;
1422 break;
1423 default:
1424 printf("Error: invalid burst length of %u specified. ",
1425 popts->burst_length);
1426 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1427 bl = 1;
1428 break;
1429 }
1430
1431 sdmode = (0
1432 | ((wr & 0x7) << 9)
1433 | ((dll_rst & 0x1) << 8)
1434 | ((mode & 0x1) << 7)
1435 | (((caslat >> 1) & 0x7) << 4)
1436 | ((bt & 0x1) << 3)
1437 | ((caslat & 1) << 2)
1438 | ((bl & 0x3) << 0)
1439 );
1440
1441 ddr->ddr_sdram_mode = (0
1442 | ((esdmode & 0xFFFF) << 16)
1443 | ((sdmode & 0xFFFF) << 0)
1444 );
1445
1446 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1447
1448 if (unq_mrs_en) { /* unique mode registers are supported */
1449 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1450 if (popts->rtt_override)
1451 rtt = popts->rtt_override_value;
1452 else
1453 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1454
1455 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1456 esdmode |= (rtt & 0x7) << 8;
1457 switch (i) {
1458 case 1:
1459 ddr->ddr_sdram_mode_3 = (0
1460 | ((esdmode & 0xFFFF) << 16)
1461 | ((sdmode & 0xFFFF) << 0)
1462 );
1463 break;
1464 case 2:
1465 ddr->ddr_sdram_mode_5 = (0
1466 | ((esdmode & 0xFFFF) << 16)
1467 | ((sdmode & 0xFFFF) << 0)
1468 );
1469 break;
1470 case 3:
1471 ddr->ddr_sdram_mode_7 = (0
1472 | ((esdmode & 0xFFFF) << 16)
1473 | ((sdmode & 0xFFFF) << 0)
1474 );
1475 break;
1476 }
1477 }
1478 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1479 ddr->ddr_sdram_mode_3);
1480 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1481 ddr->ddr_sdram_mode_5);
1482 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1483 ddr->ddr_sdram_mode_5);
1484 }
1485 }
1486
1487 #elif defined(CONFIG_SYS_FSL_DDR3)
1488 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
set_ddr_sdram_mode(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency,const unsigned int unq_mrs_en)1489 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1490 fsl_ddr_cfg_regs_t *ddr,
1491 const memctl_options_t *popts,
1492 const common_timing_params_t *common_dimm,
1493 unsigned int cas_latency,
1494 unsigned int additive_latency,
1495 const unsigned int unq_mrs_en)
1496 {
1497 int i;
1498 unsigned short esdmode; /* Extended SDRAM mode */
1499 unsigned short sdmode; /* SDRAM mode */
1500
1501 /* Mode Register - MR1 */
1502 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1503 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1504 unsigned int rtt;
1505 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1506 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1507 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1508 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1509 1=Disable (Test/Debug) */
1510
1511 /* Mode Register - MR0 */
1512 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1513 unsigned int wr = 0; /* Write Recovery */
1514 unsigned int dll_rst; /* DLL Reset */
1515 unsigned int mode; /* Normal=0 or Test=1 */
1516 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1517 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1518 unsigned int bt;
1519 unsigned int bl; /* BL: Burst Length */
1520
1521 unsigned int wr_mclk;
1522 /*
1523 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1524 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1525 * for this table
1526 */
1527 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1528
1529 if (popts->rtt_override)
1530 rtt = popts->rtt_override_value;
1531 else
1532 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1533
1534 if (additive_latency == (cas_latency - 1))
1535 al = 1;
1536 if (additive_latency == (cas_latency - 2))
1537 al = 2;
1538
1539 if (popts->quad_rank_present)
1540 dic = 1; /* output driver impedance 240/7 ohm */
1541
1542 /*
1543 * The esdmode value will also be used for writing
1544 * MR1 during write leveling for DDR3, although the
1545 * bits specifically related to the write leveling
1546 * scheme will be handled automatically by the DDR
1547 * controller. so we set the wrlvl_en = 0 here.
1548 */
1549 esdmode = (0
1550 | ((qoff & 0x1) << 12)
1551 | ((tdqs_en & 0x1) << 11)
1552 | ((rtt & 0x4) << 7) /* rtt field is split */
1553 | ((wrlvl_en & 0x1) << 7)
1554 | ((rtt & 0x2) << 5) /* rtt field is split */
1555 | ((dic & 0x2) << 4) /* DIC field is split */
1556 | ((al & 0x3) << 3)
1557 | ((rtt & 0x1) << 2) /* rtt field is split */
1558 | ((dic & 0x1) << 1) /* DIC field is split */
1559 | ((dll_en & 0x1) << 0)
1560 );
1561
1562 /*
1563 * DLL control for precharge PD
1564 * 0=slow exit DLL off (tXPDLL)
1565 * 1=fast exit DLL on (tXP)
1566 */
1567 dll_on = 1;
1568
1569 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1570 if (wr_mclk <= 16) {
1571 wr = wr_table[wr_mclk - 5];
1572 } else {
1573 printf("Error: unsupported write recovery for mode register "
1574 "wr_mclk = %d\n", wr_mclk);
1575 }
1576
1577 dll_rst = 0; /* dll no reset */
1578 mode = 0; /* normal mode */
1579
1580 /* look up table to get the cas latency bits */
1581 if (cas_latency >= 5 && cas_latency <= 16) {
1582 unsigned char cas_latency_table[] = {
1583 0x2, /* 5 clocks */
1584 0x4, /* 6 clocks */
1585 0x6, /* 7 clocks */
1586 0x8, /* 8 clocks */
1587 0xa, /* 9 clocks */
1588 0xc, /* 10 clocks */
1589 0xe, /* 11 clocks */
1590 0x1, /* 12 clocks */
1591 0x3, /* 13 clocks */
1592 0x5, /* 14 clocks */
1593 0x7, /* 15 clocks */
1594 0x9, /* 16 clocks */
1595 };
1596 caslat = cas_latency_table[cas_latency - 5];
1597 } else {
1598 printf("Error: unsupported cas latency for mode register\n");
1599 }
1600
1601 bt = 0; /* Nibble sequential */
1602
1603 switch (popts->burst_length) {
1604 case DDR_BL8:
1605 bl = 0;
1606 break;
1607 case DDR_OTF:
1608 bl = 1;
1609 break;
1610 case DDR_BC4:
1611 bl = 2;
1612 break;
1613 default:
1614 printf("Error: invalid burst length of %u specified. "
1615 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1616 popts->burst_length);
1617 bl = 1;
1618 break;
1619 }
1620
1621 sdmode = (0
1622 | ((dll_on & 0x1) << 12)
1623 | ((wr & 0x7) << 9)
1624 | ((dll_rst & 0x1) << 8)
1625 | ((mode & 0x1) << 7)
1626 | (((caslat >> 1) & 0x7) << 4)
1627 | ((bt & 0x1) << 3)
1628 | ((caslat & 1) << 2)
1629 | ((bl & 0x3) << 0)
1630 );
1631
1632 ddr->ddr_sdram_mode = (0
1633 | ((esdmode & 0xFFFF) << 16)
1634 | ((sdmode & 0xFFFF) << 0)
1635 );
1636
1637 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1638
1639 if (unq_mrs_en) { /* unique mode registers are supported */
1640 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1641 if (popts->rtt_override)
1642 rtt = popts->rtt_override_value;
1643 else
1644 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1645
1646 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1647 esdmode |= (0
1648 | ((rtt & 0x4) << 7) /* rtt field is split */
1649 | ((rtt & 0x2) << 5) /* rtt field is split */
1650 | ((rtt & 0x1) << 2) /* rtt field is split */
1651 );
1652 switch (i) {
1653 case 1:
1654 ddr->ddr_sdram_mode_3 = (0
1655 | ((esdmode & 0xFFFF) << 16)
1656 | ((sdmode & 0xFFFF) << 0)
1657 );
1658 break;
1659 case 2:
1660 ddr->ddr_sdram_mode_5 = (0
1661 | ((esdmode & 0xFFFF) << 16)
1662 | ((sdmode & 0xFFFF) << 0)
1663 );
1664 break;
1665 case 3:
1666 ddr->ddr_sdram_mode_7 = (0
1667 | ((esdmode & 0xFFFF) << 16)
1668 | ((sdmode & 0xFFFF) << 0)
1669 );
1670 break;
1671 }
1672 }
1673 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1674 ddr->ddr_sdram_mode_3);
1675 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1676 ddr->ddr_sdram_mode_5);
1677 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1678 ddr->ddr_sdram_mode_5);
1679 }
1680 }
1681
1682 #else /* !CONFIG_SYS_FSL_DDR3 */
1683
1684 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
set_ddr_sdram_mode(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency,const unsigned int unq_mrs_en)1685 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1686 fsl_ddr_cfg_regs_t *ddr,
1687 const memctl_options_t *popts,
1688 const common_timing_params_t *common_dimm,
1689 unsigned int cas_latency,
1690 unsigned int additive_latency,
1691 const unsigned int unq_mrs_en)
1692 {
1693 unsigned short esdmode; /* Extended SDRAM mode */
1694 unsigned short sdmode; /* SDRAM mode */
1695
1696 /*
1697 * FIXME: This ought to be pre-calculated in a
1698 * technology-specific routine,
1699 * e.g. compute_DDR2_mode_register(), and then the
1700 * sdmode and esdmode passed in as part of common_dimm.
1701 */
1702
1703 /* Extended Mode Register */
1704 unsigned int mrs = 0; /* Mode Register Set */
1705 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1706 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1707 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1708 unsigned int ocd = 0; /* 0x0=OCD not supported,
1709 0x7=OCD default state */
1710 unsigned int rtt;
1711 unsigned int al; /* Posted CAS# additive latency (AL) */
1712 unsigned int ods = 0; /* Output Drive Strength:
1713 0 = Full strength (18ohm)
1714 1 = Reduced strength (4ohm) */
1715 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1716 1=Disable (Test/Debug) */
1717
1718 /* Mode Register (MR) */
1719 unsigned int mr; /* Mode Register Definition */
1720 unsigned int pd; /* Power-Down Mode */
1721 unsigned int wr; /* Write Recovery */
1722 unsigned int dll_res; /* DLL Reset */
1723 unsigned int mode; /* Normal=0 or Test=1 */
1724 unsigned int caslat = 0;/* CAS# latency */
1725 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1726 unsigned int bt;
1727 unsigned int bl; /* BL: Burst Length */
1728
1729 dqs_en = !popts->dqs_config;
1730 rtt = fsl_ddr_get_rtt();
1731
1732 al = additive_latency;
1733
1734 esdmode = (0
1735 | ((mrs & 0x3) << 14)
1736 | ((outputs & 0x1) << 12)
1737 | ((rdqs_en & 0x1) << 11)
1738 | ((dqs_en & 0x1) << 10)
1739 | ((ocd & 0x7) << 7)
1740 | ((rtt & 0x2) << 5) /* rtt field is split */
1741 | ((al & 0x7) << 3)
1742 | ((rtt & 0x1) << 2) /* rtt field is split */
1743 | ((ods & 0x1) << 1)
1744 | ((dll_en & 0x1) << 0)
1745 );
1746
1747 mr = 0; /* FIXME: CHECKME */
1748
1749 /*
1750 * 0 = Fast Exit (Normal)
1751 * 1 = Slow Exit (Low Power)
1752 */
1753 pd = 0;
1754
1755 #if defined(CONFIG_SYS_FSL_DDR1)
1756 wr = 0; /* Historical */
1757 #elif defined(CONFIG_SYS_FSL_DDR2)
1758 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1759 #endif
1760 dll_res = 0;
1761 mode = 0;
1762
1763 #if defined(CONFIG_SYS_FSL_DDR1)
1764 if (1 <= cas_latency && cas_latency <= 4) {
1765 unsigned char mode_caslat_table[4] = {
1766 0x5, /* 1.5 clocks */
1767 0x2, /* 2.0 clocks */
1768 0x6, /* 2.5 clocks */
1769 0x3 /* 3.0 clocks */
1770 };
1771 caslat = mode_caslat_table[cas_latency - 1];
1772 } else {
1773 printf("Warning: unknown cas_latency %d\n", cas_latency);
1774 }
1775 #elif defined(CONFIG_SYS_FSL_DDR2)
1776 caslat = cas_latency;
1777 #endif
1778 bt = 0;
1779
1780 switch (popts->burst_length) {
1781 case DDR_BL4:
1782 bl = 2;
1783 break;
1784 case DDR_BL8:
1785 bl = 3;
1786 break;
1787 default:
1788 printf("Error: invalid burst length of %u specified. "
1789 " Defaulting to 4 beats.\n",
1790 popts->burst_length);
1791 bl = 2;
1792 break;
1793 }
1794
1795 sdmode = (0
1796 | ((mr & 0x3) << 14)
1797 | ((pd & 0x1) << 12)
1798 | ((wr & 0x7) << 9)
1799 | ((dll_res & 0x1) << 8)
1800 | ((mode & 0x1) << 7)
1801 | ((caslat & 0x7) << 4)
1802 | ((bt & 0x1) << 3)
1803 | ((bl & 0x7) << 0)
1804 );
1805
1806 ddr->ddr_sdram_mode = (0
1807 | ((esdmode & 0xFFFF) << 16)
1808 | ((sdmode & 0xFFFF) << 0)
1809 );
1810 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1811 }
1812 #endif
1813
1814 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
set_ddr_data_init(fsl_ddr_cfg_regs_t * ddr)1815 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1816 {
1817 unsigned int init_value; /* Initialization value */
1818
1819 #ifdef CONFIG_MEM_INIT_VALUE
1820 init_value = CONFIG_MEM_INIT_VALUE;
1821 #else
1822 init_value = 0xDEADBEEF;
1823 #endif
1824 ddr->ddr_data_init = init_value;
1825 }
1826
1827 /*
1828 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1829 * The old controller on the 8540/60 doesn't have this register.
1830 * Hope it's OK to set it (to 0) anyway.
1831 */
set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)1832 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1833 const memctl_options_t *popts)
1834 {
1835 unsigned int clk_adjust; /* Clock adjust */
1836 unsigned int ss_en = 0; /* Source synchronous enable */
1837
1838 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1839 /* Per FSL Application Note: AN2805 */
1840 ss_en = 1;
1841 #endif
1842 if (fsl_ddr_get_version(0) >= 0x40701) {
1843 /* clk_adjust in 5-bits on T-series and LS-series */
1844 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1845 } else {
1846 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1847 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1848 }
1849
1850 ddr->ddr_sdram_clk_cntl = (0
1851 | ((ss_en & 0x1) << 31)
1852 | clk_adjust
1853 );
1854 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1855 }
1856
1857 /* DDR Initialization Address (DDR_INIT_ADDR) */
set_ddr_init_addr(fsl_ddr_cfg_regs_t * ddr)1858 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1859 {
1860 unsigned int init_addr = 0; /* Initialization address */
1861
1862 ddr->ddr_init_addr = init_addr;
1863 }
1864
1865 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t * ddr)1866 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1867 {
1868 unsigned int uia = 0; /* Use initialization address */
1869 unsigned int init_ext_addr = 0; /* Initialization address */
1870
1871 ddr->ddr_init_ext_addr = (0
1872 | ((uia & 0x1) << 31)
1873 | (init_ext_addr & 0xF)
1874 );
1875 }
1876
1877 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
set_timing_cfg_4(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)1878 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1879 const memctl_options_t *popts)
1880 {
1881 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1882 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1883 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1884 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1885 unsigned int trwt_mclk = 0; /* ext_rwt */
1886 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1887
1888 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1889 if (popts->burst_length == DDR_BL8) {
1890 /* We set BL/2 for fixed BL8 */
1891 rrt = 0; /* BL/2 clocks */
1892 wwt = 0; /* BL/2 clocks */
1893 } else {
1894 /* We need to set BL/2 + 2 to BC4 and OTF */
1895 rrt = 2; /* BL/2 + 2 clocks */
1896 wwt = 2; /* BL/2 + 2 clocks */
1897 }
1898 #endif
1899 #ifdef CONFIG_SYS_FSL_DDR4
1900 dll_lock = 2; /* tDLLK = 1024 clocks */
1901 #elif defined(CONFIG_SYS_FSL_DDR3)
1902 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1903 #endif
1904
1905 if (popts->trwt_override)
1906 trwt_mclk = popts->trwt;
1907
1908 ddr->timing_cfg_4 = (0
1909 | ((rwt & 0xf) << 28)
1910 | ((wrt & 0xf) << 24)
1911 | ((rrt & 0xf) << 20)
1912 | ((wwt & 0xf) << 16)
1913 | ((trwt_mclk & 0xc) << 12)
1914 | (dll_lock & 0x3)
1915 );
1916 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1917 }
1918
1919 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
set_timing_cfg_5(fsl_ddr_cfg_regs_t * ddr,unsigned int cas_latency)1920 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1921 {
1922 unsigned int rodt_on = 0; /* Read to ODT on */
1923 unsigned int rodt_off = 0; /* Read to ODT off */
1924 unsigned int wodt_on = 0; /* Write to ODT on */
1925 unsigned int wodt_off = 0; /* Write to ODT off */
1926
1927 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1928 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1929 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1930 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1931 if (cas_latency >= wr_lat)
1932 rodt_on = cas_latency - wr_lat + 1;
1933 rodt_off = 4; /* 4 clocks */
1934 wodt_on = 1; /* 1 clocks */
1935 wodt_off = 4; /* 4 clocks */
1936 #endif
1937
1938 ddr->timing_cfg_5 = (0
1939 | ((rodt_on & 0x1f) << 24)
1940 | ((rodt_off & 0x7) << 20)
1941 | ((wodt_on & 0x1f) << 12)
1942 | ((wodt_off & 0x7) << 8)
1943 );
1944 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1945 }
1946
1947 #ifdef CONFIG_SYS_FSL_DDR4
set_timing_cfg_6(fsl_ddr_cfg_regs_t * ddr)1948 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1949 {
1950 unsigned int hs_caslat = 0;
1951 unsigned int hs_wrlat = 0;
1952 unsigned int hs_wrrec = 0;
1953 unsigned int hs_clkadj = 0;
1954 unsigned int hs_wrlvl_start = 0;
1955
1956 ddr->timing_cfg_6 = (0
1957 | ((hs_caslat & 0x1f) << 24)
1958 | ((hs_wrlat & 0x1f) << 19)
1959 | ((hs_wrrec & 0x1f) << 12)
1960 | ((hs_clkadj & 0x1f) << 6)
1961 | ((hs_wrlvl_start & 0x1f) << 0)
1962 );
1963 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1964 }
1965
set_timing_cfg_7(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const common_timing_params_t * common_dimm)1966 static void set_timing_cfg_7(const unsigned int ctrl_num,
1967 fsl_ddr_cfg_regs_t *ddr,
1968 const common_timing_params_t *common_dimm)
1969 {
1970 unsigned int txpr, tcksre, tcksrx;
1971 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
1972 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
1973
1974 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1975 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1976 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1977
1978 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1979 if (mclk_ps >= 935) {
1980 /* parity latency 4 clocks in case of 1600/1866/2133 */
1981 par_lat = 4;
1982 } else if (mclk_ps >= 833) {
1983 /* parity latency 5 clocks for DDR4-2400 */
1984 par_lat = 5;
1985 } else {
1986 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1987 }
1988 }
1989
1990 cs_to_cmd = 0;
1991
1992 if (txpr <= 200)
1993 cke_rst = 0;
1994 else if (txpr <= 256)
1995 cke_rst = 1;
1996 else if (txpr <= 512)
1997 cke_rst = 2;
1998 else
1999 cke_rst = 3;
2000
2001 if (tcksre <= 19)
2002 cksre = tcksre - 5;
2003 else
2004 cksre = 15;
2005
2006 if (tcksrx <= 19)
2007 cksrx = tcksrx - 5;
2008 else
2009 cksrx = 15;
2010
2011 ddr->timing_cfg_7 = (0
2012 | ((cke_rst & 0x3) << 28)
2013 | ((cksre & 0xf) << 24)
2014 | ((cksrx & 0xf) << 20)
2015 | ((par_lat & 0xf) << 16)
2016 | ((cs_to_cmd & 0xf) << 4)
2017 );
2018 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2019 }
2020
set_timing_cfg_8(const unsigned int ctrl_num,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency)2021 static void set_timing_cfg_8(const unsigned int ctrl_num,
2022 fsl_ddr_cfg_regs_t *ddr,
2023 const memctl_options_t *popts,
2024 const common_timing_params_t *common_dimm,
2025 unsigned int cas_latency)
2026 {
2027 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2028 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2029 unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2030 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2031 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2032
2033 rwt_bg = cas_latency + 2 + 4 - wr_lat;
2034 if (rwt_bg < tccdl)
2035 rwt_bg = tccdl - rwt_bg;
2036 else
2037 rwt_bg = 0;
2038
2039 wrt_bg = wr_lat + 4 + 1 - cas_latency;
2040 if (wrt_bg < tccdl)
2041 wrt_bg = tccdl - wrt_bg;
2042 else
2043 wrt_bg = 0;
2044
2045 if (popts->burst_length == DDR_BL8) {
2046 rrt_bg = tccdl - 4;
2047 wwt_bg = tccdl - 4;
2048 } else {
2049 rrt_bg = tccdl - 2;
2050 wwt_bg = tccdl - 2;
2051 }
2052
2053 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2054 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2055 if (popts->otf_burst_chop_en)
2056 wrtord_bg += 2;
2057
2058 pre_all_rec = 0;
2059
2060 ddr->timing_cfg_8 = (0
2061 | ((rwt_bg & 0xf) << 28)
2062 | ((wrt_bg & 0xf) << 24)
2063 | ((rrt_bg & 0xf) << 20)
2064 | ((wwt_bg & 0xf) << 16)
2065 | ((acttoact_bg & 0xf) << 12)
2066 | ((wrtord_bg & 0xf) << 8)
2067 | ((pre_all_rec & 0x1f) << 0)
2068 );
2069
2070 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2071 }
2072
set_timing_cfg_9(fsl_ddr_cfg_regs_t * ddr)2073 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
2074 {
2075 ddr->timing_cfg_9 = 0;
2076 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2077 }
2078
2079 /* This function needs to be called after set_ddr_sdram_cfg() is called */
set_ddr_dq_mapping(fsl_ddr_cfg_regs_t * ddr,const dimm_params_t * dimm_params)2080 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2081 const dimm_params_t *dimm_params)
2082 {
2083 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2084 int i;
2085
2086 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2087 if (dimm_params[i].n_ranks)
2088 break;
2089 }
2090 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2091 puts("DDR error: no DIMM found!\n");
2092 return;
2093 }
2094
2095 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2096 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2097 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2098 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2099 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2100
2101 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2102 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2103 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2104 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2105 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2106
2107 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2108 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2109 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2110 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2111 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2112
2113 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2114 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2115 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2116 (acc_ecc_en ? 0 :
2117 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2118 dimm_params[i].dq_mapping_ors;
2119
2120 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2121 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2122 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2123 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2124 }
set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)2125 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2126 const memctl_options_t *popts)
2127 {
2128 int rd_pre;
2129
2130 rd_pre = popts->quad_rank_present ? 1 : 0;
2131
2132 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2133
2134 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2135 }
2136 #endif /* CONFIG_SYS_FSL_DDR4 */
2137
2138 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
set_ddr_zq_cntl(fsl_ddr_cfg_regs_t * ddr,unsigned int zq_en)2139 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2140 {
2141 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2142 /* Normal Operation Full Calibration Time (tZQoper) */
2143 unsigned int zqoper = 0;
2144 /* Normal Operation Short Calibration Time (tZQCS) */
2145 unsigned int zqcs = 0;
2146 #ifdef CONFIG_SYS_FSL_DDR4
2147 unsigned int zqcs_init;
2148 #endif
2149
2150 if (zq_en) {
2151 #ifdef CONFIG_SYS_FSL_DDR4
2152 zqinit = 10; /* 1024 clocks */
2153 zqoper = 9; /* 512 clocks */
2154 zqcs = 7; /* 128 clocks */
2155 zqcs_init = 5; /* 1024 refresh sequences */
2156 #else
2157 zqinit = 9; /* 512 clocks */
2158 zqoper = 8; /* 256 clocks */
2159 zqcs = 6; /* 64 clocks */
2160 #endif
2161 }
2162
2163 ddr->ddr_zq_cntl = (0
2164 | ((zq_en & 0x1) << 31)
2165 | ((zqinit & 0xF) << 24)
2166 | ((zqoper & 0xF) << 16)
2167 | ((zqcs & 0xF) << 8)
2168 #ifdef CONFIG_SYS_FSL_DDR4
2169 | ((zqcs_init & 0xF) << 0)
2170 #endif
2171 );
2172 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2173 }
2174
2175 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t * ddr,unsigned int wrlvl_en,const memctl_options_t * popts)2176 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2177 const memctl_options_t *popts)
2178 {
2179 /*
2180 * First DQS pulse rising edge after margining mode
2181 * is programmed (tWL_MRD)
2182 */
2183 unsigned int wrlvl_mrd = 0;
2184 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2185 unsigned int wrlvl_odten = 0;
2186 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2187 unsigned int wrlvl_dqsen = 0;
2188 /* WRLVL_SMPL: Write leveling sample time */
2189 unsigned int wrlvl_smpl = 0;
2190 /* WRLVL_WLR: Write leveling repeition time */
2191 unsigned int wrlvl_wlr = 0;
2192 /* WRLVL_START: Write leveling start time */
2193 unsigned int wrlvl_start = 0;
2194
2195 /* suggest enable write leveling for DDR3 due to fly-by topology */
2196 if (wrlvl_en) {
2197 /* tWL_MRD min = 40 nCK, we set it 64 */
2198 wrlvl_mrd = 0x6;
2199 /* tWL_ODTEN 128 */
2200 wrlvl_odten = 0x7;
2201 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2202 wrlvl_dqsen = 0x5;
2203 /*
2204 * Write leveling sample time at least need 6 clocks
2205 * higher than tWLO to allow enough time for progagation
2206 * delay and sampling the prime data bits.
2207 */
2208 wrlvl_smpl = 0xf;
2209 /*
2210 * Write leveling repetition time
2211 * at least tWLO + 6 clocks clocks
2212 * we set it 64
2213 */
2214 wrlvl_wlr = 0x6;
2215 /*
2216 * Write leveling start time
2217 * The value use for the DQS_ADJUST for the first sample
2218 * when write leveling is enabled. It probably needs to be
2219 * overridden per platform.
2220 */
2221 wrlvl_start = 0x8;
2222 /*
2223 * Override the write leveling sample and start time
2224 * according to specific board
2225 */
2226 if (popts->wrlvl_override) {
2227 wrlvl_smpl = popts->wrlvl_sample;
2228 wrlvl_start = popts->wrlvl_start;
2229 }
2230 }
2231
2232 ddr->ddr_wrlvl_cntl = (0
2233 | ((wrlvl_en & 0x1) << 31)
2234 | ((wrlvl_mrd & 0x7) << 24)
2235 | ((wrlvl_odten & 0x7) << 20)
2236 | ((wrlvl_dqsen & 0x7) << 16)
2237 | ((wrlvl_smpl & 0xf) << 12)
2238 | ((wrlvl_wlr & 0x7) << 8)
2239 | ((wrlvl_start & 0x1F) << 0)
2240 );
2241 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2242 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2243 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2244 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2245 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2246
2247 }
2248
2249 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
set_ddr_sr_cntr(fsl_ddr_cfg_regs_t * ddr,unsigned int sr_it)2250 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2251 {
2252 /* Self Refresh Idle Threshold */
2253 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2254 }
2255
set_ddr_eor(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)2256 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2257 {
2258 if (popts->addr_hash) {
2259 ddr->ddr_eor = 0x40000000; /* address hash enable */
2260 puts("Address hashing enabled.\n");
2261 }
2262 }
2263
set_ddr_cdr1(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)2264 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2265 {
2266 ddr->ddr_cdr1 = popts->ddr_cdr1;
2267 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2268 }
2269
set_ddr_cdr2(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)2270 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2271 {
2272 ddr->ddr_cdr2 = popts->ddr_cdr2;
2273 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2274 }
2275
2276 unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t * ddr)2277 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2278 {
2279 unsigned int res = 0;
2280
2281 /*
2282 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2283 * not set at the same time.
2284 */
2285 if (ddr->ddr_sdram_cfg & 0x10000000
2286 && ddr->ddr_sdram_cfg & 0x00008000) {
2287 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2288 " should not be set at the same time.\n");
2289 res++;
2290 }
2291
2292 return res;
2293 }
2294
2295 unsigned int
compute_fsl_memctl_config_regs(const unsigned int ctrl_num,const memctl_options_t * popts,fsl_ddr_cfg_regs_t * ddr,const common_timing_params_t * common_dimm,const dimm_params_t * dimm_params,unsigned int dbw_cap_adj,unsigned int size_only)2296 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2297 const memctl_options_t *popts,
2298 fsl_ddr_cfg_regs_t *ddr,
2299 const common_timing_params_t *common_dimm,
2300 const dimm_params_t *dimm_params,
2301 unsigned int dbw_cap_adj,
2302 unsigned int size_only)
2303 {
2304 unsigned int i;
2305 unsigned int cas_latency;
2306 unsigned int additive_latency;
2307 unsigned int sr_it;
2308 unsigned int zq_en;
2309 unsigned int wrlvl_en;
2310 unsigned int ip_rev = 0;
2311 unsigned int unq_mrs_en = 0;
2312 int cs_en = 1;
2313 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2314 unsigned int ddr_freq;
2315 #endif
2316 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2317 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2318 defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2319 struct ccsr_ddr __iomem *ddrc;
2320
2321 switch (ctrl_num) {
2322 case 0:
2323 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2324 break;
2325 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2326 case 1:
2327 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2328 break;
2329 #endif
2330 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2331 case 2:
2332 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2333 break;
2334 #endif
2335 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2336 case 3:
2337 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2338 break;
2339 #endif
2340 default:
2341 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2342 return 1;
2343 }
2344 #endif
2345
2346 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2347
2348 if (common_dimm == NULL) {
2349 printf("Error: subset DIMM params struct null pointer\n");
2350 return 1;
2351 }
2352
2353 /*
2354 * Process overrides first.
2355 *
2356 * FIXME: somehow add dereated caslat to this
2357 */
2358 cas_latency = (popts->cas_latency_override)
2359 ? popts->cas_latency_override_value
2360 : common_dimm->lowest_common_spd_caslat;
2361
2362 additive_latency = (popts->additive_latency_override)
2363 ? popts->additive_latency_override_value
2364 : common_dimm->additive_latency;
2365
2366 sr_it = (popts->auto_self_refresh_en)
2367 ? popts->sr_it
2368 : 0;
2369 /* ZQ calibration */
2370 zq_en = (popts->zq_en) ? 1 : 0;
2371 /* write leveling */
2372 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2373
2374 /* Chip Select Memory Bounds (CSn_BNDS) */
2375 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2376 unsigned long long ea, sa;
2377 unsigned int cs_per_dimm
2378 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2379 unsigned int dimm_number
2380 = i / cs_per_dimm;
2381 unsigned long long rank_density
2382 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2383
2384 if (dimm_params[dimm_number].n_ranks == 0) {
2385 debug("Skipping setup of CS%u "
2386 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2387 continue;
2388 }
2389 if (popts->memctl_interleaving) {
2390 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2391 case FSL_DDR_CS0_CS1_CS2_CS3:
2392 break;
2393 case FSL_DDR_CS0_CS1:
2394 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2395 if (i > 1)
2396 cs_en = 0;
2397 break;
2398 case FSL_DDR_CS2_CS3:
2399 default:
2400 if (i > 0)
2401 cs_en = 0;
2402 break;
2403 }
2404 sa = common_dimm->base_address;
2405 ea = sa + common_dimm->total_mem - 1;
2406 } else if (!popts->memctl_interleaving) {
2407 /*
2408 * If memory interleaving between controllers is NOT
2409 * enabled, the starting address for each memory
2410 * controller is distinct. However, because rank
2411 * interleaving is enabled, the starting and ending
2412 * addresses of the total memory on that memory
2413 * controller needs to be programmed into its
2414 * respective CS0_BNDS.
2415 */
2416 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2417 case FSL_DDR_CS0_CS1_CS2_CS3:
2418 sa = common_dimm->base_address;
2419 ea = sa + common_dimm->total_mem - 1;
2420 break;
2421 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2422 if ((i >= 2) && (dimm_number == 0)) {
2423 sa = dimm_params[dimm_number].base_address +
2424 2 * rank_density;
2425 ea = sa + 2 * rank_density - 1;
2426 } else {
2427 sa = dimm_params[dimm_number].base_address;
2428 ea = sa + 2 * rank_density - 1;
2429 }
2430 break;
2431 case FSL_DDR_CS0_CS1:
2432 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2433 sa = dimm_params[dimm_number].base_address;
2434 ea = sa + rank_density - 1;
2435 if (i != 1)
2436 sa += (i % cs_per_dimm) * rank_density;
2437 ea += (i % cs_per_dimm) * rank_density;
2438 } else {
2439 sa = 0;
2440 ea = 0;
2441 }
2442 if (i == 0)
2443 ea += rank_density;
2444 break;
2445 case FSL_DDR_CS2_CS3:
2446 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2447 sa = dimm_params[dimm_number].base_address;
2448 ea = sa + rank_density - 1;
2449 if (i != 3)
2450 sa += (i % cs_per_dimm) * rank_density;
2451 ea += (i % cs_per_dimm) * rank_density;
2452 } else {
2453 sa = 0;
2454 ea = 0;
2455 }
2456 if (i == 2)
2457 ea += (rank_density >> dbw_cap_adj);
2458 break;
2459 default: /* No bank(chip-select) interleaving */
2460 sa = dimm_params[dimm_number].base_address;
2461 ea = sa + rank_density - 1;
2462 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2463 sa += (i % cs_per_dimm) * rank_density;
2464 ea += (i % cs_per_dimm) * rank_density;
2465 } else {
2466 sa = 0;
2467 ea = 0;
2468 }
2469 break;
2470 }
2471 }
2472
2473 sa >>= 24;
2474 ea >>= 24;
2475
2476 if (cs_en) {
2477 ddr->cs[i].bnds = (0
2478 | ((sa & 0xffff) << 16) /* starting address */
2479 | ((ea & 0xffff) << 0) /* ending address */
2480 );
2481 } else {
2482 /* setting bnds to 0xffffffff for inactive CS */
2483 ddr->cs[i].bnds = 0xffffffff;
2484 }
2485
2486 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2487 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2488 set_csn_config_2(i, ddr);
2489 }
2490
2491 /*
2492 * In the case we only need to compute the ddr sdram size, we only need
2493 * to set csn registers, so return from here.
2494 */
2495 if (size_only)
2496 return 0;
2497
2498 set_ddr_eor(ddr, popts);
2499
2500 #if !defined(CONFIG_SYS_FSL_DDR1)
2501 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2502 #endif
2503
2504 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2505 additive_latency);
2506 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2507 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2508 cas_latency, additive_latency);
2509
2510 set_ddr_cdr1(ddr, popts);
2511 set_ddr_cdr2(ddr, popts);
2512 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2513 ip_rev = fsl_ddr_get_version(ctrl_num);
2514 if (ip_rev > 0x40400)
2515 unq_mrs_en = 1;
2516
2517 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2518 ddr->debug[18] = popts->cswl_override;
2519
2520 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2521 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2522 cas_latency, additive_latency, unq_mrs_en);
2523 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2524 #ifdef CONFIG_SYS_FSL_DDR4
2525 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2526 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2527 #endif
2528 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2529 set_ddr_data_init(ddr);
2530 set_ddr_sdram_clk_cntl(ddr, popts);
2531 set_ddr_init_addr(ddr);
2532 set_ddr_init_ext_addr(ddr);
2533 set_timing_cfg_4(ddr, popts);
2534 set_timing_cfg_5(ddr, cas_latency);
2535 #ifdef CONFIG_SYS_FSL_DDR4
2536 set_ddr_sdram_cfg_3(ddr, popts);
2537 set_timing_cfg_6(ddr);
2538 set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2539 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2540 set_timing_cfg_9(ddr);
2541 set_ddr_dq_mapping(ddr, dimm_params);
2542 #endif
2543
2544 set_ddr_zq_cntl(ddr, zq_en);
2545 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2546
2547 set_ddr_sr_cntr(ddr, sr_it);
2548
2549 set_ddr_sdram_rcw(ddr, popts, common_dimm);
2550
2551 #ifdef CONFIG_SYS_FSL_DDR_EMU
2552 /* disble DDR training for emulator */
2553 ddr->debug[2] = 0x00000400;
2554 ddr->debug[4] = 0xff800800;
2555 ddr->debug[5] = 0x08000800;
2556 ddr->debug[6] = 0x08000800;
2557 ddr->debug[7] = 0x08000800;
2558 ddr->debug[8] = 0x08000800;
2559 #endif
2560 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2561 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2562 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2563 #endif
2564
2565 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2566 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2567 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2568 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2569 if (has_erratum_a008378()) {
2570 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2571 IS_DBI(ddr->ddr_sdram_cfg_3)) {
2572 ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2573 ddr->debug[28] |= (0x9 << 20);
2574 }
2575 }
2576 #endif
2577
2578 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2579 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2580 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2581 ddr->debug[28] &= 0xff0fff00;
2582 if (ddr_freq <= 1333)
2583 ddr->debug[28] |= 0x0080006a;
2584 else if (ddr_freq <= 1600)
2585 ddr->debug[28] |= 0x0070006f;
2586 else if (ddr_freq <= 1867)
2587 ddr->debug[28] |= 0x00700076;
2588 else if (ddr_freq <= 2133)
2589 ddr->debug[28] |= 0x0060007b;
2590 if (popts->cpo_sample)
2591 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2592 popts->cpo_sample;
2593 #endif
2594
2595 return check_fsl_memctl_config_regs(ddr);
2596 }
2597
2598 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2599 /*
2600 * This additional workaround of A009942 checks the condition to determine if
2601 * the CPO value set by the existing A009942 workaround needs to be updated.
2602 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2603 * expected optimal value, the optimal value is highly board dependent.
2604 */
erratum_a009942_check_cpo(void)2605 void erratum_a009942_check_cpo(void)
2606 {
2607 struct ccsr_ddr __iomem *ddr =
2608 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2609 u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2610 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2611 u32 cpo_max = cpo_min;
2612 u32 sdram_cfg, i, tmp, lanes, ddr_type;
2613 bool update_cpo = false, has_ecc = false;
2614
2615 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2616 if (sdram_cfg & SDRAM_CFG_32_BE)
2617 lanes = 4;
2618 else if (sdram_cfg & SDRAM_CFG_16_BE)
2619 lanes = 2;
2620 else
2621 lanes = 8;
2622
2623 if (sdram_cfg & SDRAM_CFG_ECC_EN)
2624 has_ecc = true;
2625
2626 /* determine the maximum and minimum CPO values */
2627 for (i = 9; i < 9 + lanes / 2; i++) {
2628 cpo = ddr_in32(&ddr->debug[i]);
2629 cpo_e = cpo >> 24;
2630 cpo_o = (cpo >> 8) & 0xff;
2631 tmp = min(cpo_e, cpo_o);
2632 if (tmp < cpo_min)
2633 cpo_min = tmp;
2634 tmp = max(cpo_e, cpo_o);
2635 if (tmp > cpo_max)
2636 cpo_max = tmp;
2637 }
2638
2639 if (has_ecc) {
2640 cpo = ddr_in32(&ddr->debug[13]);
2641 cpo = cpo >> 24;
2642 if (cpo < cpo_min)
2643 cpo_min = cpo;
2644 if (cpo > cpo_max)
2645 cpo_max = cpo;
2646 }
2647
2648 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2649 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2650 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2651 cpo_target);
2652 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2653
2654 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2655 SDRAM_CFG_SDRAM_TYPE_SHIFT;
2656 if (ddr_type == SDRAM_TYPE_DDR4)
2657 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2658 else if (ddr_type == SDRAM_TYPE_DDR3)
2659 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2660
2661 if (update_cpo) {
2662 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2663 printf("in <board>/ddr.c to optimize cpo\n");
2664 }
2665 }
2666 #endif
2667