1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright 2008-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun# 4*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ 8*4882a593Smuzhiyun lc_common_dimm_params.o 9*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ 10*4882a593Smuzhiyun lc_common_dimm_params.o 11*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ 12*4882a593Smuzhiyun lc_common_dimm_params.o 13*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \ 14*4882a593Smuzhiyun lc_common_dimm_params.o 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunifdef CONFIG_DDR_SPD 17*4882a593SmuzhiyunSPD := y 18*4882a593Smuzhiyunendif 19*4882a593Smuzhiyunifdef CONFIG_SPD_EEPROM 20*4882a593SmuzhiyunSPD := y 21*4882a593Smuzhiyunendif 22*4882a593Smuzhiyunifdef SPD 23*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o 24*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o 25*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o 26*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o 27*4882a593Smuzhiyunendif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunobj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o 30*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o 31*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o 32*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o 33*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o 34*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o 35*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o 36*4882a593Smuzhiyunobj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o 37