1*4882a593Smuzhiyunconfig SYS_FSL_DDR 2*4882a593Smuzhiyun bool 3*4882a593Smuzhiyun help 4*4882a593Smuzhiyun Select Freescale General DDR driver, shared between most Freescale 5*4882a593Smuzhiyun PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- 6*4882a593Smuzhiyun based Layerscape SoCs (such as ls2080a). 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunconfig SYS_FSL_MMDC 9*4882a593Smuzhiyun bool 10*4882a593Smuzhiyun help 11*4882a593Smuzhiyun Select Freescale Multi Mode DDR controller (MMDC). 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunconfig SYS_FSL_DDR_BE 14*4882a593Smuzhiyun bool 15*4882a593Smuzhiyun help 16*4882a593Smuzhiyun Access DDR registers in big-endian 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunconfig SYS_FSL_DDR_LE 19*4882a593Smuzhiyun bool 20*4882a593Smuzhiyun help 21*4882a593Smuzhiyun Access DDR registers in little-endian 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunmenu "Freescale DDR controllers" 24*4882a593Smuzhiyun depends on SYS_FSL_DDR 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunconfig SYS_NUM_DDR_CTLRS 27*4882a593Smuzhiyun int "Maximum DDR controllers" 28*4882a593Smuzhiyun default 3 if ARCH_LS2080A || \ 29*4882a593Smuzhiyun ARCH_T4240 30*4882a593Smuzhiyun default 2 if ARCH_B4860 || \ 31*4882a593Smuzhiyun ARCH_BSC9132 || \ 32*4882a593Smuzhiyun ARCH_MPC8572 || \ 33*4882a593Smuzhiyun ARCH_MPC8641 || \ 34*4882a593Smuzhiyun ARCH_P4080 || \ 35*4882a593Smuzhiyun ARCH_P5020 || \ 36*4882a593Smuzhiyun ARCH_P5040 || \ 37*4882a593Smuzhiyun ARCH_T4160 38*4882a593Smuzhiyun default 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunconfig SYS_FSL_DDR_VER 41*4882a593Smuzhiyun int 42*4882a593Smuzhiyun default 50 if SYS_FSL_DDR_VER_50 43*4882a593Smuzhiyun default 47 if SYS_FSL_DDR_VER_47 44*4882a593Smuzhiyun default 46 if SYS_FSL_DDR_VER_46 45*4882a593Smuzhiyun default 44 if SYS_FSL_DDR_VER_44 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunconfig SYS_FSL_DDR_VER_50 48*4882a593Smuzhiyun bool 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunconfig SYS_FSL_DDR_VER_47 51*4882a593Smuzhiyun bool 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunconfig SYS_FSL_DDR_VER_46 54*4882a593Smuzhiyun bool 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig SYS_FSL_DDR_VER_44 57*4882a593Smuzhiyun bool 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunconfig SYS_FSL_DDRC_GEN1 60*4882a593Smuzhiyun bool 61*4882a593Smuzhiyun help 62*4882a593Smuzhiyun Enable Freescale DDR controller. 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunconfig SYS_FSL_DDRC_GEN2 65*4882a593Smuzhiyun bool 66*4882a593Smuzhiyun depends on !MPC86xx 67*4882a593Smuzhiyun help 68*4882a593Smuzhiyun Enable Freescale DDR2 controller. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunconfig SYS_FSL_DDRC_86XX_GEN2 71*4882a593Smuzhiyun bool 72*4882a593Smuzhiyun depends on MPC86xx 73*4882a593Smuzhiyun help 74*4882a593Smuzhiyun Enable Freescale DDR2 controller for MPC86xx SoCs. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunconfig SYS_FSL_DDRC_GEN3 77*4882a593Smuzhiyun bool 78*4882a593Smuzhiyun depends on PPC 79*4882a593Smuzhiyun help 80*4882a593Smuzhiyun Enable Freescale DDR3 controller for PowerPC SoCs. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunconfig SYS_FSL_DDRC_ARM_GEN3 83*4882a593Smuzhiyun bool 84*4882a593Smuzhiyun depends on ARM 85*4882a593Smuzhiyun help 86*4882a593Smuzhiyun Enable Freescale DDR3 controller for ARM SoCs. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyunconfig SYS_FSL_DDRC_GEN4 89*4882a593Smuzhiyun bool 90*4882a593Smuzhiyun help 91*4882a593Smuzhiyun Enable Freescale DDR4 controller. 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunconfig SYS_FSL_HAS_DDR4 94*4882a593Smuzhiyun bool 95*4882a593Smuzhiyun 96*4882a593Smuzhiyunconfig SYS_FSL_HAS_DDR3 97*4882a593Smuzhiyun bool 98*4882a593Smuzhiyun 99*4882a593Smuzhiyunconfig SYS_FSL_HAS_DDR2 100*4882a593Smuzhiyun bool 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunconfig SYS_FSL_HAS_DDR1 103*4882a593Smuzhiyun bool 104*4882a593Smuzhiyun 105*4882a593Smuzhiyunchoice 106*4882a593Smuzhiyun prompt "DDR technology" 107*4882a593Smuzhiyun default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 108*4882a593Smuzhiyun default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 109*4882a593Smuzhiyun default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 110*4882a593Smuzhiyun default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunconfig SYS_FSL_DDR4 113*4882a593Smuzhiyun bool "Freescale DDR4 controller" 114*4882a593Smuzhiyun depends on SYS_FSL_HAS_DDR4 115*4882a593Smuzhiyun select SYS_FSL_DDRC_GEN4 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunconfig SYS_FSL_DDR3 118*4882a593Smuzhiyun bool "Freescale DDR3 controller" 119*4882a593Smuzhiyun depends on SYS_FSL_HAS_DDR3 120*4882a593Smuzhiyun select SYS_FSL_DDRC_GEN3 if PPC 121*4882a593Smuzhiyun select SYS_FSL_DDRC_ARM_GEN3 if ARM 122*4882a593Smuzhiyun 123*4882a593Smuzhiyunconfig SYS_FSL_DDR2 124*4882a593Smuzhiyun bool "Freescale DDR2 controller" 125*4882a593Smuzhiyun depends on SYS_FSL_HAS_DDR2 126*4882a593Smuzhiyun select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) 127*4882a593Smuzhiyun select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx 128*4882a593Smuzhiyun 129*4882a593Smuzhiyunconfig SYS_FSL_DDR1 130*4882a593Smuzhiyun bool "Freescale DDR1 controller" 131*4882a593Smuzhiyun depends on SYS_FSL_HAS_DDR1 132*4882a593Smuzhiyun select SYS_FSL_DDRC_GEN1 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunendchoice 135*4882a593Smuzhiyun 136*4882a593Smuzhiyunendmenu 137*4882a593Smuzhiyun 138*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A008378 139*4882a593Smuzhiyun bool 140*4882a593Smuzhiyun 141*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A008511 142*4882a593Smuzhiyun bool 143*4882a593Smuzhiyun 144*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A009663 145*4882a593Smuzhiyun bool 146*4882a593Smuzhiyun 147*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A009801 148*4882a593Smuzhiyun bool 149*4882a593Smuzhiyun 150*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A009803 151*4882a593Smuzhiyun bool 152*4882a593Smuzhiyun 153*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A009942 154*4882a593Smuzhiyun bool 155*4882a593Smuzhiyun 156*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A010165 157*4882a593Smuzhiyun bool 158*4882a593Smuzhiyun 159*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_NMG_DDR120 160*4882a593Smuzhiyun bool 161*4882a593Smuzhiyun 162*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_DDR_115 163*4882a593Smuzhiyun bool 164*4882a593Smuzhiyun 165*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_DDR111_DDR134 166*4882a593Smuzhiyun bool 167*4882a593Smuzhiyun 168*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_DDR_A003 169*4882a593Smuzhiyun bool 170*4882a593Smuzhiyun 171*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_DDR_A003474 172*4882a593Smuzhiyun bool 173