1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __JR_H 9*4882a593Smuzhiyun #define __JR_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/compiler.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define JR_SIZE 4 14*4882a593Smuzhiyun /* Timeout currently defined as 90 sec */ 15*4882a593Smuzhiyun #define CONFIG_SEC_DEQ_TIMEOUT 90000000U 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DEFAULT_JR_ID 0 18*4882a593Smuzhiyun #define DEFAULT_JR_LIODN 0 19*4882a593Smuzhiyun #define DEFAULT_IRQ 0 /* Interrupts not to be configured */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ 22*4882a593Smuzhiyun #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ 23*4882a593Smuzhiyun #define MCFGR_PS_SHIFT 16 24*4882a593Smuzhiyun #define MCFGR_AWCACHE_SHIFT 8 25*4882a593Smuzhiyun #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 26*4882a593Smuzhiyun #define MCFGR_ARCACHE_SHIFT 12 27*4882a593Smuzhiyun #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define JR_INTMASK 0x00000001 30*4882a593Smuzhiyun #define JRCR_RESET 0x01 31*4882a593Smuzhiyun #define JRINT_ERR_HALT_INPROGRESS 0x4 32*4882a593Smuzhiyun #define JRINT_ERR_HALT_MASK 0xc 33*4882a593Smuzhiyun #define JRNSLIODN_SHIFT 16 34*4882a593Smuzhiyun #define JRNSLIODN_MASK 0x0fff0000 35*4882a593Smuzhiyun #define JRSLIODN_SHIFT 0 36*4882a593Smuzhiyun #define JRSLIODN_MASK 0x00000fff 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define JQ_DEQ_ERR -1 39*4882a593Smuzhiyun #define JQ_DEQ_TO_ERR -2 40*4882a593Smuzhiyun #define JQ_ENQ_ERR -3 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct op_ring { 43*4882a593Smuzhiyun phys_addr_t desc; 44*4882a593Smuzhiyun uint32_t status; 45*4882a593Smuzhiyun } __packed; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct jr_info { 48*4882a593Smuzhiyun void (*callback)(uint32_t status, void *arg); 49*4882a593Smuzhiyun phys_addr_t desc_phys_addr; 50*4882a593Smuzhiyun uint32_t desc_len; 51*4882a593Smuzhiyun uint32_t op_done; 52*4882a593Smuzhiyun void *arg; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct jobring { 56*4882a593Smuzhiyun int jq_id; 57*4882a593Smuzhiyun int irq; 58*4882a593Smuzhiyun int liodn; 59*4882a593Smuzhiyun /* Head is the index where software would enq the descriptor in 60*4882a593Smuzhiyun * the i/p ring 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun int head; 63*4882a593Smuzhiyun /* Tail index would be used by s/w ehile enqueuing to determine if 64*4882a593Smuzhiyun * there is any space left in the s/w maintained i/p rings 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun /* Also in case of deq tail will be incremented only in case of 67*4882a593Smuzhiyun * in-order job completion 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun int tail; 70*4882a593Smuzhiyun /* Read index of the output ring. It may not match with tail in case 71*4882a593Smuzhiyun * of out of order completetion 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun int read_idx; 74*4882a593Smuzhiyun /* Write index to input ring. Would be always equal to head */ 75*4882a593Smuzhiyun int write_idx; 76*4882a593Smuzhiyun /* Size of the rings. */ 77*4882a593Smuzhiyun int size; 78*4882a593Smuzhiyun /* Op ring size aligned to cache line size */ 79*4882a593Smuzhiyun int op_size; 80*4882a593Smuzhiyun /* The ip and output rings have to be accessed by SEC. So the 81*4882a593Smuzhiyun * pointers will ahve to point to the housekeeping region provided 82*4882a593Smuzhiyun * by SEC 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun /*Circular Ring of i/p descriptors */ 85*4882a593Smuzhiyun dma_addr_t *input_ring; 86*4882a593Smuzhiyun /* Circular Ring of o/p descriptors */ 87*4882a593Smuzhiyun /* Circula Ring containing info regarding descriptors in i/p 88*4882a593Smuzhiyun * and o/p ring 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun /* This ring can be on the stack */ 91*4882a593Smuzhiyun struct jr_info info[JR_SIZE]; 92*4882a593Smuzhiyun struct op_ring *output_ring; 93*4882a593Smuzhiyun /* Offset in CCSR to the SEC engine to which this JR belongs */ 94*4882a593Smuzhiyun uint32_t sec_offset; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct result { 99*4882a593Smuzhiyun int done; 100*4882a593Smuzhiyun uint32_t status; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun void caam_jr_strstatus(u32 status); 104*4882a593Smuzhiyun int run_descriptor_jr(uint32_t *desc); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif 107