1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk-uclass.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <misc.h>
11*4882a593Smuzhiyun #include <asm/arch-tegra/bpmp_abi.h>
12*4882a593Smuzhiyun
tegra186_clk_get_rate(struct clk * clk)13*4882a593Smuzhiyun static ulong tegra186_clk_get_rate(struct clk *clk)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun struct mrq_clk_request req;
16*4882a593Smuzhiyun struct mrq_clk_response resp;
17*4882a593Smuzhiyun int ret;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
20*4882a593Smuzhiyun clk->id);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
25*4882a593Smuzhiyun sizeof(resp));
26*4882a593Smuzhiyun if (ret < 0)
27*4882a593Smuzhiyun return ret;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return resp.clk_get_rate.rate;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
tegra186_clk_set_rate(struct clk * clk,ulong rate)32*4882a593Smuzhiyun static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct mrq_clk_request req;
35*4882a593Smuzhiyun struct mrq_clk_response resp;
36*4882a593Smuzhiyun int ret;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
39*4882a593Smuzhiyun clk->dev, clk->id);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
42*4882a593Smuzhiyun req.clk_set_rate.rate = rate;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
45*4882a593Smuzhiyun sizeof(resp));
46*4882a593Smuzhiyun if (ret < 0)
47*4882a593Smuzhiyun return ret;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return resp.clk_set_rate.rate;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
tegra186_clk_en_dis(struct clk * clk,enum mrq_reset_commands cmd)52*4882a593Smuzhiyun static int tegra186_clk_en_dis(struct clk *clk,
53*4882a593Smuzhiyun enum mrq_reset_commands cmd)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct mrq_clk_request req;
56*4882a593Smuzhiyun struct mrq_clk_response resp;
57*4882a593Smuzhiyun int ret;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun req.cmd_and_id = (cmd << 24) | clk->id;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
62*4882a593Smuzhiyun sizeof(resp));
63*4882a593Smuzhiyun if (ret < 0)
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
tegra186_clk_enable(struct clk * clk)69*4882a593Smuzhiyun static int tegra186_clk_enable(struct clk *clk)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
72*4882a593Smuzhiyun clk->id);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
tegra186_clk_disable(struct clk * clk)77*4882a593Smuzhiyun static int tegra186_clk_disable(struct clk *clk)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
80*4882a593Smuzhiyun clk->id);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static struct clk_ops tegra186_clk_ops = {
86*4882a593Smuzhiyun .get_rate = tegra186_clk_get_rate,
87*4882a593Smuzhiyun .set_rate = tegra186_clk_set_rate,
88*4882a593Smuzhiyun .enable = tegra186_clk_enable,
89*4882a593Smuzhiyun .disable = tegra186_clk_disable,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
tegra186_clk_probe(struct udevice * dev)92*4882a593Smuzhiyun static int tegra186_clk_probe(struct udevice *dev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun debug("%s(dev=%p)\n", __func__, dev);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun U_BOOT_DRIVER(tegra186_clk) = {
100*4882a593Smuzhiyun .name = "tegra186_clk",
101*4882a593Smuzhiyun .id = UCLASS_CLK,
102*4882a593Smuzhiyun .probe = tegra186_clk_probe,
103*4882a593Smuzhiyun .ops = &tegra186_clk_ops,
104*4882a593Smuzhiyun };
105