1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk-uclass.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <asm/arch/clock.h>
11*4882a593Smuzhiyun #include <asm/arch-tegra/clk_rst.h>
12*4882a593Smuzhiyun
tegra_car_clk_request(struct clk * clk)13*4882a593Smuzhiyun static int tegra_car_clk_request(struct clk *clk)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
16*4882a593Smuzhiyun clk->id);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Note that the first PERIPH_ID_COUNT clock IDs (where the value
20*4882a593Smuzhiyun * varies per SoC) are the peripheral clocks, which use a numbering
21*4882a593Smuzhiyun * scheme that matches HW registers 1:1. There are other clock IDs
22*4882a593Smuzhiyun * beyond this that are assigned arbitrarily by the Tegra CAR DT
23*4882a593Smuzhiyun * binding. Due to the implementation of this driver, it currently
24*4882a593Smuzhiyun * only supports the peripheral IDs.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun if (clk->id >= PERIPH_ID_COUNT)
27*4882a593Smuzhiyun return -EINVAL;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
tegra_car_clk_free(struct clk * clk)32*4882a593Smuzhiyun static int tegra_car_clk_free(struct clk *clk)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
35*4882a593Smuzhiyun clk->id);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
tegra_car_clk_get_rate(struct clk * clk)40*4882a593Smuzhiyun static ulong tegra_car_clk_get_rate(struct clk *clk)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun enum clock_id parent;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
45*4882a593Smuzhiyun clk->id);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun parent = clock_get_periph_parent(clk->id);
48*4882a593Smuzhiyun return clock_get_periph_rate(clk->id, parent);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
tegra_car_clk_set_rate(struct clk * clk,ulong rate)51*4882a593Smuzhiyun static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun enum clock_id parent;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
56*4882a593Smuzhiyun clk->dev, clk->id);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun parent = clock_get_periph_parent(clk->id);
59*4882a593Smuzhiyun return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
tegra_car_clk_enable(struct clk * clk)62*4882a593Smuzhiyun static int tegra_car_clk_enable(struct clk *clk)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
65*4882a593Smuzhiyun clk->id);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun clock_enable(clk->id);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
tegra_car_clk_disable(struct clk * clk)72*4882a593Smuzhiyun static int tegra_car_clk_disable(struct clk *clk)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
75*4882a593Smuzhiyun clk->id);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun clock_disable(clk->id);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static struct clk_ops tegra_car_clk_ops = {
83*4882a593Smuzhiyun .request = tegra_car_clk_request,
84*4882a593Smuzhiyun .free = tegra_car_clk_free,
85*4882a593Smuzhiyun .get_rate = tegra_car_clk_get_rate,
86*4882a593Smuzhiyun .set_rate = tegra_car_clk_set_rate,
87*4882a593Smuzhiyun .enable = tegra_car_clk_enable,
88*4882a593Smuzhiyun .disable = tegra_car_clk_disable,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
tegra_car_clk_probe(struct udevice * dev)91*4882a593Smuzhiyun static int tegra_car_clk_probe(struct udevice *dev)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun debug("%s(dev=%p)\n", __func__, dev);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun U_BOOT_DRIVER(tegra_car_clk) = {
99*4882a593Smuzhiyun .name = "tegra_car_clk",
100*4882a593Smuzhiyun .id = UCLASS_CLK,
101*4882a593Smuzhiyun .probe = tegra_car_clk_probe,
102*4882a593Smuzhiyun .ops = &tegra_car_clk_ops,
103*4882a593Smuzhiyun };
104