xref: /OK3568_Linux_fs/u-boot/drivers/clk/clk_fixed_rate.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk-uclass.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun struct clk_fixed_rate {
12*4882a593Smuzhiyun 	unsigned long fixed_rate;
13*4882a593Smuzhiyun };
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
16*4882a593Smuzhiyun 
clk_fixed_rate_get_rate(struct clk * clk)17*4882a593Smuzhiyun static ulong clk_fixed_rate_get_rate(struct clk *clk)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun 	if (clk->id != 0)
20*4882a593Smuzhiyun 		return -EINVAL;
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	return to_clk_fixed_rate(clk->dev)->fixed_rate;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun const struct clk_ops clk_fixed_rate_ops = {
26*4882a593Smuzhiyun 	.get_rate = clk_fixed_rate_get_rate,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
clk_fixed_rate_ofdata_to_platdata(struct udevice * dev)29*4882a593Smuzhiyun static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun #if !CONFIG_IS_ENABLED(OF_PLATDATA)
32*4882a593Smuzhiyun 	to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev,
33*4882a593Smuzhiyun 							"clock-frequency", 0);
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static const struct udevice_id clk_fixed_rate_match[] = {
40*4882a593Smuzhiyun 	{
41*4882a593Smuzhiyun 		.compatible = "fixed-clock",
42*4882a593Smuzhiyun 	},
43*4882a593Smuzhiyun 	{ /* sentinel */ }
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun U_BOOT_DRIVER(clk_fixed_rate) = {
47*4882a593Smuzhiyun 	.name = "fixed_rate_clock",
48*4882a593Smuzhiyun 	.id = UCLASS_CLK,
49*4882a593Smuzhiyun 	.of_match = clk_fixed_rate_match,
50*4882a593Smuzhiyun 	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
51*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
52*4882a593Smuzhiyun 	.ops = &clk_fixed_rate_ops,
53*4882a593Smuzhiyun };
54