xref: /OK3568_Linux_fs/u-boot/drivers/clk/at91/clk-utmi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 Atmel Corporation
3*4882a593Smuzhiyun  *               Wenyou.Yang <wenyou.yang@atmel.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <clk-uclass.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <mach/at91_pmc.h>
13*4882a593Smuzhiyun #include "pmc.h"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define UTMI_FIXED_MUL		40
18*4882a593Smuzhiyun 
utmi_clk_enable(struct clk * clk)19*4882a593Smuzhiyun static int utmi_clk_enable(struct clk *clk)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
22*4882a593Smuzhiyun 	struct at91_pmc *pmc = plat->reg_base;
23*4882a593Smuzhiyun 	u32 tmp;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	if (readl(&pmc->sr) & AT91_PMC_LOCKU)
26*4882a593Smuzhiyun 		return 0;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	tmp = readl(&pmc->uckr);
29*4882a593Smuzhiyun 	tmp |= AT91_PMC_UPLLEN |
30*4882a593Smuzhiyun 	       AT91_PMC_UPLLCOUNT |
31*4882a593Smuzhiyun 	       AT91_PMC_BIASEN;
32*4882a593Smuzhiyun 	writel(tmp, &pmc->uckr);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	while (!(readl(&pmc->sr) & AT91_PMC_LOCKU))
35*4882a593Smuzhiyun 		;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun 
utmi_clk_get_rate(struct clk * clk)40*4882a593Smuzhiyun static ulong utmi_clk_get_rate(struct clk *clk)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static struct clk_ops utmi_clk_ops = {
46*4882a593Smuzhiyun 	.enable = utmi_clk_enable,
47*4882a593Smuzhiyun 	.get_rate = utmi_clk_get_rate,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
utmi_clk_probe(struct udevice * dev)50*4882a593Smuzhiyun static int utmi_clk_probe(struct udevice *dev)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	return at91_pmc_core_probe(dev);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun static const struct udevice_id utmi_clk_match[] = {
56*4882a593Smuzhiyun 	{ .compatible = "atmel,at91sam9x5-clk-utmi" },
57*4882a593Smuzhiyun 	{}
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
61*4882a593Smuzhiyun 	.name = "at91sam9x5-utmi-clk",
62*4882a593Smuzhiyun 	.id = UCLASS_CLK,
63*4882a593Smuzhiyun 	.of_match = utmi_clk_match,
64*4882a593Smuzhiyun 	.probe = utmi_clk_probe,
65*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
66*4882a593Smuzhiyun 	.ops = &utmi_clk_ops,
67*4882a593Smuzhiyun };
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