1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Atmel Corporation
3*4882a593Smuzhiyun * Wenyou.Yang <wenyou.yang@atmel.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <clk-uclass.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <mach/at91_pmc.h>
13*4882a593Smuzhiyun #include "pmc.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define PERIPHERAL_ID_MIN 2
16*4882a593Smuzhiyun #define PERIPHERAL_ID_MAX 31
17*4882a593Smuzhiyun #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun enum periph_clk_type {
20*4882a593Smuzhiyun CLK_PERIPH_AT91RM9200 = 0,
21*4882a593Smuzhiyun CLK_PERIPH_AT91SAM9X5,
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun /**
24*4882a593Smuzhiyun * sam9x5_periph_clk_bind() - for the periph clock driver
25*4882a593Smuzhiyun * Recursively bind its children as clk devices.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * @return: 0 on success, or negative error code on failure
28*4882a593Smuzhiyun */
sam9x5_periph_clk_bind(struct udevice * dev)29*4882a593Smuzhiyun static int sam9x5_periph_clk_bind(struct udevice *dev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun return at91_clk_sub_device_bind(dev, "periph-clk");
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct udevice_id sam9x5_periph_clk_match[] = {
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun .compatible = "atmel,at91rm9200-clk-peripheral",
37*4882a593Smuzhiyun .data = CLK_PERIPH_AT91RM9200,
38*4882a593Smuzhiyun },
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun .compatible = "atmel,at91sam9x5-clk-peripheral",
41*4882a593Smuzhiyun .data = CLK_PERIPH_AT91SAM9X5,
42*4882a593Smuzhiyun },
43*4882a593Smuzhiyun {}
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun U_BOOT_DRIVER(sam9x5_periph_clk) = {
47*4882a593Smuzhiyun .name = "sam9x5-periph-clk",
48*4882a593Smuzhiyun .id = UCLASS_MISC,
49*4882a593Smuzhiyun .of_match = sam9x5_periph_clk_match,
50*4882a593Smuzhiyun .bind = sam9x5_periph_clk_bind,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*---------------------------------------------------------*/
54*4882a593Smuzhiyun
periph_clk_enable(struct clk * clk)55*4882a593Smuzhiyun static int periph_clk_enable(struct clk *clk)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct pmc_platdata *plat = dev_get_platdata(clk->dev);
58*4882a593Smuzhiyun struct at91_pmc *pmc = plat->reg_base;
59*4882a593Smuzhiyun enum periph_clk_type clk_type;
60*4882a593Smuzhiyun void *addr;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (clk->id < PERIPHERAL_ID_MIN)
63*4882a593Smuzhiyun return -1;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
66*4882a593Smuzhiyun if (clk_type == CLK_PERIPH_AT91RM9200) {
67*4882a593Smuzhiyun addr = &pmc->pcer;
68*4882a593Smuzhiyun if (clk->id > PERIPHERAL_ID_MAX)
69*4882a593Smuzhiyun addr = &pmc->pcer1;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun setbits_le32(addr, PERIPHERAL_MASK(clk->id));
72*4882a593Smuzhiyun } else {
73*4882a593Smuzhiyun writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
74*4882a593Smuzhiyun setbits_le32(&pmc->pcr,
75*4882a593Smuzhiyun AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
periph_get_rate(struct clk * clk)81*4882a593Smuzhiyun static ulong periph_get_rate(struct clk *clk)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct udevice *dev;
84*4882a593Smuzhiyun struct clk clk_dev;
85*4882a593Smuzhiyun ulong clk_rate;
86*4882a593Smuzhiyun int ret;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun dev = dev_get_parent(clk->dev);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &clk_dev);
91*4882a593Smuzhiyun if (ret)
92*4882a593Smuzhiyun return ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun clk_rate = clk_get_rate(&clk_dev);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun clk_free(&clk_dev);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return clk_rate;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static struct clk_ops periph_clk_ops = {
102*4882a593Smuzhiyun .of_xlate = at91_clk_of_xlate,
103*4882a593Smuzhiyun .enable = periph_clk_enable,
104*4882a593Smuzhiyun .get_rate = periph_get_rate,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun U_BOOT_DRIVER(clk_periph) = {
108*4882a593Smuzhiyun .name = "periph-clk",
109*4882a593Smuzhiyun .id = UCLASS_CLK,
110*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
111*4882a593Smuzhiyun .probe = at91_clk_probe,
112*4882a593Smuzhiyun .ops = &periph_clk_ops,
113*4882a593Smuzhiyun };
114