1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Atmel Corporation 3*4882a593Smuzhiyun * Wenyou.Yang <wenyou.yang@atmel.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <clk-uclass.h> 10*4882a593Smuzhiyun #include <dm.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 13*4882a593Smuzhiyun at91_master_clk_get_rate(struct clk * clk)14*4882a593Smuzhiyunstatic ulong at91_master_clk_get_rate(struct clk *clk) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun return gd->arch.mck_rate_hz; 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun static struct clk_ops at91_master_clk_ops = { 20*4882a593Smuzhiyun .get_rate = at91_master_clk_get_rate, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static const struct udevice_id at91_master_clk_match[] = { 24*4882a593Smuzhiyun { .compatible = "atmel,at91rm9200-clk-master" }, 25*4882a593Smuzhiyun { .compatible = "atmel,at91sam9x5-clk-master" }, 26*4882a593Smuzhiyun {} 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun U_BOOT_DRIVER(at91_master_clk) = { 30*4882a593Smuzhiyun .name = "at91-master-clk", 31*4882a593Smuzhiyun .id = UCLASS_CLK, 32*4882a593Smuzhiyun .of_match = at91_master_clk_match, 33*4882a593Smuzhiyun .ops = &at91_master_clk_ops, 34*4882a593Smuzhiyun }; 35