1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Atmel Corporation
3*4882a593Smuzhiyun * Wenyou.Yang <wenyou.yang@atmel.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <clk-uclass.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <mach/at91_pmc.h>
13*4882a593Smuzhiyun #include "pmc.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
main_osc_clk_enable(struct clk * clk)17*4882a593Smuzhiyun static int main_osc_clk_enable(struct clk *clk)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun struct pmc_platdata *plat = dev_get_platdata(clk->dev);
20*4882a593Smuzhiyun struct at91_pmc *pmc = plat->reg_base;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
23*4882a593Smuzhiyun return 0;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun return -EINVAL;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
main_osc_clk_get_rate(struct clk * clk)28*4882a593Smuzhiyun static ulong main_osc_clk_get_rate(struct clk *clk)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun return gd->arch.main_clk_rate_hz;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct clk_ops main_osc_clk_ops = {
34*4882a593Smuzhiyun .enable = main_osc_clk_enable,
35*4882a593Smuzhiyun .get_rate = main_osc_clk_get_rate,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
main_osc_clk_probe(struct udevice * dev)38*4882a593Smuzhiyun static int main_osc_clk_probe(struct udevice *dev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return at91_pmc_core_probe(dev);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const struct udevice_id main_osc_clk_match[] = {
44*4882a593Smuzhiyun { .compatible = "atmel,at91sam9x5-clk-main" },
45*4882a593Smuzhiyun {}
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
49*4882a593Smuzhiyun .name = "at91sam9x5-main-osc-clk",
50*4882a593Smuzhiyun .id = UCLASS_CLK,
51*4882a593Smuzhiyun .of_match = main_osc_clk_match,
52*4882a593Smuzhiyun .probe = main_osc_clk_probe,
53*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
54*4882a593Smuzhiyun .ops = &main_osc_clk_ops,
55*4882a593Smuzhiyun };
56