1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. 3*4882a593Smuzhiyun * Author: Tor Krill <tor@excito.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef SATA_SIL3114_H 9*4882a593Smuzhiyun #define SATA_SIL3114_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct sata_ioports { 12*4882a593Smuzhiyun unsigned long cmd_addr; 13*4882a593Smuzhiyun unsigned long data_addr; 14*4882a593Smuzhiyun unsigned long error_addr; 15*4882a593Smuzhiyun unsigned long feature_addr; 16*4882a593Smuzhiyun unsigned long nsect_addr; 17*4882a593Smuzhiyun unsigned long lbal_addr; 18*4882a593Smuzhiyun unsigned long lbam_addr; 19*4882a593Smuzhiyun unsigned long lbah_addr; 20*4882a593Smuzhiyun unsigned long device_addr; 21*4882a593Smuzhiyun unsigned long status_addr; 22*4882a593Smuzhiyun unsigned long command_addr; 23*4882a593Smuzhiyun unsigned long altstatus_addr; 24*4882a593Smuzhiyun unsigned long ctl_addr; 25*4882a593Smuzhiyun unsigned long bmdma_addr; 26*4882a593Smuzhiyun unsigned long scr_addr; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct sata_port { 30*4882a593Smuzhiyun unsigned char port_no; /* primary=0, secondary=1 */ 31*4882a593Smuzhiyun struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ 32*4882a593Smuzhiyun unsigned char ctl_reg; 33*4882a593Smuzhiyun unsigned char last_ctl; 34*4882a593Smuzhiyun unsigned char port_state; /* 1-port is available and */ 35*4882a593Smuzhiyun /* 0-port is not available */ 36*4882a593Smuzhiyun unsigned char dev_mask; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Missing ata defines */ 40*4882a593Smuzhiyun #define ATA_CMD_STANDBY 0xE2 41*4882a593Smuzhiyun #define ATA_CMD_STANDBYNOW1 0xE0 42*4882a593Smuzhiyun #define ATA_CMD_IDLE 0xE3 43*4882a593Smuzhiyun #define ATA_CMD_IDLEIMMEDIATE 0xE1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Defines for SIL3114 chip */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* PCI defines */ 48*4882a593Smuzhiyun #define SIL_VEND_ID 0x1095 49*4882a593Smuzhiyun #define SIL3114_DEVICE_ID 0x3114 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* some vendor specific registers */ 52*4882a593Smuzhiyun #define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */ 53*4882a593Smuzhiyun #define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22) 54*4882a593Smuzhiyun #define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23) 55*4882a593Smuzhiyun #define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24) 56*4882a593Smuzhiyun #define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* internal registers mapped by BAR5 */ 59*4882a593Smuzhiyun /* SATA Control*/ 60*4882a593Smuzhiyun #define VND_SCONTROL_CH0 0x100 61*4882a593Smuzhiyun #define VND_SCONTROL_CH1 0x180 62*4882a593Smuzhiyun #define VND_SCONTROL_CH2 0x300 63*4882a593Smuzhiyun #define VND_SCONTROL_CH3 0x380 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SATA_SC_IPM_T2P (1<<16) 66*4882a593Smuzhiyun #define SATA_SC_IPM_T2S (2<<16) 67*4882a593Smuzhiyun #define SATA_SC_SPD_1_5 (1<<4) 68*4882a593Smuzhiyun #define SATA_SC_SPD_3_0 (2<<4) 69*4882a593Smuzhiyun #define SATA_SC_DET_RST (1) /* ATA Reset sequence */ 70*4882a593Smuzhiyun #define SATA_SC_DET_PDIS (4) /* PHY Disable */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* SATA Status */ 73*4882a593Smuzhiyun #define VND_SSTATUS_CH0 0x104 74*4882a593Smuzhiyun #define VND_SSTATUS_CH1 0x184 75*4882a593Smuzhiyun #define VND_SSTATUS_CH2 0x304 76*4882a593Smuzhiyun #define VND_SSTATUS_CH3 0x384 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define SATA_SS_IPM_ACTIVE (1<<8) 79*4882a593Smuzhiyun #define SATA_SS_IPM_PARTIAL (2<<8) 80*4882a593Smuzhiyun #define SATA_SS_IPM_SLUMBER (6<<8) 81*4882a593Smuzhiyun #define SATA_SS_SPD_1_5 (1<<4) 82*4882a593Smuzhiyun #define SATA_SS_SPD_3_0 (2<<4) 83*4882a593Smuzhiyun #define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */ 84*4882a593Smuzhiyun #define SATA_DET_PRES (3) /* Device presence and active PHY */ 85*4882a593Smuzhiyun #define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Task file registers in BAR5 mapping */ 88*4882a593Smuzhiyun #define VND_TF0_CH0 0x80 89*4882a593Smuzhiyun #define VND_TF0_CH1 0xc0 90*4882a593Smuzhiyun #define VND_TF0_CH2 0x280 91*4882a593Smuzhiyun #define VND_TF0_CH3 0x2c0 92*4882a593Smuzhiyun #define VND_TF1_CH0 0x88 93*4882a593Smuzhiyun #define VND_TF1_CH1 0xc8 94*4882a593Smuzhiyun #define VND_TF1_CH2 0x288 95*4882a593Smuzhiyun #define VND_TF1_CH3 0x2c8 96*4882a593Smuzhiyun #define VND_TF2_CH0 0x88 97*4882a593Smuzhiyun #define VND_TF2_CH1 0xc8 98*4882a593Smuzhiyun #define VND_TF2_CH2 0x288 99*4882a593Smuzhiyun #define VND_TF2_CH3 0x2c8 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define VND_BMDMA_CH0 0x00 102*4882a593Smuzhiyun #define VND_BMDMA_CH1 0x08 103*4882a593Smuzhiyun #define VND_BMDMA_CH2 0x200 104*4882a593Smuzhiyun #define VND_BMDMA_CH3 0x208 105*4882a593Smuzhiyun #define VND_BMDMA2_CH0 0x10 106*4882a593Smuzhiyun #define VND_BMDMA2_CH1 0x18 107*4882a593Smuzhiyun #define VND_BMDMA2_CH2 0x210 108*4882a593Smuzhiyun #define VND_BMDMA2_CH3 0x218 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* FIFO control */ 111*4882a593Smuzhiyun #define VND_FIFOCFG_CH0 0x40 112*4882a593Smuzhiyun #define VND_FIFOCFG_CH1 0x44 113*4882a593Smuzhiyun #define VND_FIFOCFG_CH2 0x240 114*4882a593Smuzhiyun #define VND_FIFOCFG_CH3 0x244 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Task File configuration and status */ 117*4882a593Smuzhiyun #define VND_TF_CNST_CH0 0xa0 118*4882a593Smuzhiyun #define VND_TF_CNST_CH1 0xe0 119*4882a593Smuzhiyun #define VND_TF_CNST_CH2 0x2a0 120*4882a593Smuzhiyun #define VND_TF_CNST_CH3 0x2e0 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define VND_TF_CNST_BFCMD (1<<1) 123*4882a593Smuzhiyun #define VND_TF_CNST_CHNRST (1<<2) 124*4882a593Smuzhiyun #define VND_TF_CNST_VDMA (1<<10) 125*4882a593Smuzhiyun #define VND_TF_CNST_INTST (1<<11) 126*4882a593Smuzhiyun #define VND_TF_CNST_WDTO (1<<12) 127*4882a593Smuzhiyun #define VND_TF_CNST_WDEN (1<<13) 128*4882a593Smuzhiyun #define VND_TF_CNST_WDIEN (1<<14) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* for testing */ 131*4882a593Smuzhiyun #define VND_SSDR 0x04c /* System Software Data Register */ 132*4882a593Smuzhiyun #define VND_FMACS 0x050 /* Flash Memory Address control and status */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif 135