1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Freescale iMX51 ATA driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on code by:
7*4882a593Smuzhiyun * Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on code from original FSL ATA driver, which is
10*4882a593Smuzhiyun * part of eCos, the Embedded Configurable Operating System.
11*4882a593Smuzhiyun * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <common.h>
17*4882a593Smuzhiyun #include <command.h>
18*4882a593Smuzhiyun #include <config.h>
19*4882a593Smuzhiyun #include <asm/byteorder.h>
20*4882a593Smuzhiyun #include <asm/io.h>
21*4882a593Smuzhiyun #include <ide.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
24*4882a593Smuzhiyun #include <asm/arch/clock.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* MXC ATA register offsets */
27*4882a593Smuzhiyun struct mxc_ata_config_regs {
28*4882a593Smuzhiyun u8 time_off; /* 0x00 */
29*4882a593Smuzhiyun u8 time_on;
30*4882a593Smuzhiyun u8 time_1;
31*4882a593Smuzhiyun u8 time_2w;
32*4882a593Smuzhiyun u8 time_2r;
33*4882a593Smuzhiyun u8 time_ax;
34*4882a593Smuzhiyun u8 time_pio_rdx;
35*4882a593Smuzhiyun u8 time_4;
36*4882a593Smuzhiyun u8 time_9;
37*4882a593Smuzhiyun u8 time_m;
38*4882a593Smuzhiyun u8 time_jn;
39*4882a593Smuzhiyun u8 time_d;
40*4882a593Smuzhiyun u8 time_k;
41*4882a593Smuzhiyun u8 time_ack;
42*4882a593Smuzhiyun u8 time_env;
43*4882a593Smuzhiyun u8 time_udma_rdx;
44*4882a593Smuzhiyun u8 time_zah; /* 0x10 */
45*4882a593Smuzhiyun u8 time_mlix;
46*4882a593Smuzhiyun u8 time_dvh;
47*4882a593Smuzhiyun u8 time_dzfs;
48*4882a593Smuzhiyun u8 time_dvs;
49*4882a593Smuzhiyun u8 time_cvh;
50*4882a593Smuzhiyun u8 time_ss;
51*4882a593Smuzhiyun u8 time_cyc;
52*4882a593Smuzhiyun u32 fifo_data_32; /* 0x18 */
53*4882a593Smuzhiyun u32 fifo_data_16;
54*4882a593Smuzhiyun u32 fifo_fill;
55*4882a593Smuzhiyun u32 ata_control;
56*4882a593Smuzhiyun u32 interrupt_pending;
57*4882a593Smuzhiyun u32 interrupt_enable;
58*4882a593Smuzhiyun u32 interrupt_clear;
59*4882a593Smuzhiyun u32 fifo_alarm;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct mxc_data_hdd_regs {
63*4882a593Smuzhiyun u32 drive_data; /* 0xa0 */
64*4882a593Smuzhiyun u32 drive_features;
65*4882a593Smuzhiyun u32 drive_sector_count;
66*4882a593Smuzhiyun u32 drive_sector_num;
67*4882a593Smuzhiyun u32 drive_cyl_low;
68*4882a593Smuzhiyun u32 drive_cyl_high;
69*4882a593Smuzhiyun u32 drive_dev_head;
70*4882a593Smuzhiyun u32 command;
71*4882a593Smuzhiyun u32 status;
72*4882a593Smuzhiyun u32 alt_status;
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* PIO timing table */
76*4882a593Smuzhiyun #define NR_PIO_SPECS 5
77*4882a593Smuzhiyun static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
78*4882a593Smuzhiyun static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
79*4882a593Smuzhiyun static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
80*4882a593Smuzhiyun static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
81*4882a593Smuzhiyun static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
set_ata_bus_timing(unsigned char mode)84*4882a593Smuzhiyun static void set_ata_bus_timing(unsigned char mode)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct mxc_ata_config_regs *ata_regs;
89*4882a593Smuzhiyun ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (mode >= NR_PIO_SPECS)
92*4882a593Smuzhiyun return;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Write TIME_OFF/ON/1/2W */
95*4882a593Smuzhiyun writeb(3, &ata_regs->time_off);
96*4882a593Smuzhiyun writeb(3, &ata_regs->time_on);
97*4882a593Smuzhiyun writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
98*4882a593Smuzhiyun writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Write TIME_2R/AX/RDX/4 */
101*4882a593Smuzhiyun writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
102*4882a593Smuzhiyun writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
103*4882a593Smuzhiyun writeb(1, &ata_regs->time_pio_rdx);
104*4882a593Smuzhiyun writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
107*4882a593Smuzhiyun writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
ide_preinit(void)110*4882a593Smuzhiyun int ide_preinit(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct mxc_ata_config_regs *ata_regs;
113*4882a593Smuzhiyun ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* 46.3.3.4 @ FSL iMX51 manual */
116*4882a593Smuzhiyun /* FIFO normal op., drive reset */
117*4882a593Smuzhiyun writel(0x80, &ata_regs->ata_control);
118*4882a593Smuzhiyun /* FIFO normal op., drive not reset */
119*4882a593Smuzhiyun writel(0xc0, &ata_regs->ata_control);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Configure the PIO timing */
122*4882a593Smuzhiyun set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* 46.3.3.4 @ FSL iMX51 manual */
125*4882a593Smuzhiyun /* Drive not reset, IORDY handshake */
126*4882a593Smuzhiyun writel(0x41, &ata_regs->ata_control);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130