1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2021, Rockchip Electronics Co., Ltd
4 *
5 * Rockchip SARADC driver for U-Boot
6 */
7
8 #include <common.h>
9 #include <adc.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <asm/io.h>
14 #include <reset.h>
15
16 #define SARADC2_EN_END_INT BIT(0)
17 #define SARADC2_START BIT(4)
18 #define SARADC2_SINGLE_MODE BIT(5)
19
20 #define SARADC_TIMEOUT (100 * 1000)
21
22 struct rockchip_saradc_regs {
23 u32 conv_con;
24 u32 t_pd_soc;
25 u32 t_as_soc;
26 u32 t_das_soc;
27 u32 t_sel_soc;
28 u32 high_comp0;
29 u32 high_comp1;
30 u32 high_comp2;
31 u32 high_comp3;
32 u32 high_comp4;
33 u32 high_comp5;
34 u32 reserved0044;
35 u32 high_comp7;
36 u32 high_comp8;
37 u32 high_comp9;
38 u32 high_comp10;
39 u32 high_comp11;
40 u32 high_comp12;
41 u32 high_comp13;
42 u32 high_comp14;
43 u32 high_comp15;
44 u32 low_comp0;
45 u32 low_comp1;
46 u32 low_comp2;
47 u32 low_comp3;
48 u32 low_comp4;
49 u32 low_comp5;
50 u32 low_comp6;
51 u32 low_comp7;
52 u32 low_comp8;
53 u32 low_comp9;
54 u32 low_comp10;
55 u32 low_comp11;
56 u32 low_comp12;
57 u32 low_comp13;
58 u32 low_comp14;
59 u32 low_comp15;
60 u32 debounce;
61 u32 ht_int_en;
62 u32 lt_int_en;
63 u32 reserved0160[24];
64 u32 mt_int_en;
65 u32 end_int_en;
66 u32 st_con;
67 u32 status;
68 u32 end_int_st;
69 u32 ht_int_st;
70 u32 lt_int_st;
71 u32 mt_int_st;
72 u32 data0;
73 u32 data1;
74 u32 data2;
75 u32 data3;
76 u32 data4;
77 u32 data5;
78 u32 data6;
79 u32 data7;
80 u32 data8;
81 u32 data9;
82 u32 data10;
83 u32 data11;
84 u32 data12;
85 u32 data13;
86 u32 data14;
87 u32 data15;
88 u32 auto_ch_en;
89 };
90
91 struct rockchip_saradc_data {
92 int num_bits;
93 int num_channels;
94 unsigned long clk_rate;
95 };
96
97 struct rockchip_saradc_priv {
98 struct rockchip_saradc_regs *regs;
99 int active_channel;
100 const struct rockchip_saradc_data *data;
101 struct reset_ctl rst;
102 };
103
rockchip_saradc_channel_data(struct udevice * dev,int channel,unsigned int * data)104 static int rockchip_saradc_channel_data(struct udevice *dev, int channel,
105 unsigned int *data)
106 {
107 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
108 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
109
110 if (channel != priv->active_channel) {
111 pr_err("Requested channel is not active!");
112 return -EINVAL;
113 }
114
115 /* Clear irq */
116 writel(0x1, &priv->regs->end_int_st);
117
118 *data = readl(&priv->regs->data0 + priv->active_channel);
119 *data &= uc_pdata->data_mask;
120
121 return 0;
122 }
123
rockchip_saradc_start_channel(struct udevice * dev,int channel)124 static int rockchip_saradc_start_channel(struct udevice *dev, int channel)
125 {
126 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
127 int val;
128
129 if (channel < 0 || channel >= priv->data->num_channels) {
130 pr_err("Requested channel is invalid!");
131 return -EINVAL;
132 }
133
134 #if CONFIG_IS_ENABLED(DM_RESET)
135 reset_assert(&priv->rst);
136 udelay(10);
137 reset_deassert(&priv->rst);
138 #endif
139 writel(0x20, &priv->regs->t_pd_soc);
140 writel(0xc, &priv->regs->t_das_soc);
141 val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
142 writel(val, &priv->regs->end_int_en);
143 val = SARADC2_START | SARADC2_SINGLE_MODE | channel;
144 writel(val << 16 | val, &priv->regs->conv_con);
145
146 udelay(100);
147
148 priv->active_channel = channel;
149
150 return 0;
151 }
152
rockchip_saradc_stop(struct udevice * dev)153 static int rockchip_saradc_stop(struct udevice *dev)
154 {
155 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
156
157 priv->active_channel = -1;
158
159 return 0;
160 }
161
rockchip_saradc_probe(struct udevice * dev)162 static int rockchip_saradc_probe(struct udevice *dev)
163 {
164 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
165 struct clk clk;
166 int ret;
167
168 #if CONFIG_IS_ENABLED(DM_RESET)
169 ret = reset_get_by_name(dev, "saradc-apb", &priv->rst);
170 if (ret) {
171 debug("reset_get_by_name() failed: %d\n", ret);
172 return ret;
173 }
174 #endif
175
176 ret = clk_get_by_index(dev, 0, &clk);
177 if (ret)
178 return ret;
179
180 ret = clk_set_rate(&clk, priv->data->clk_rate);
181 if (IS_ERR_VALUE(ret))
182 return ret;
183
184 /* Wait until pll stable */
185 mdelay(5);
186
187 priv->active_channel = -1;
188
189 return 0;
190 }
191
rockchip_saradc_ofdata_to_platdata(struct udevice * dev)192 static int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
193 {
194 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
195 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
196 struct rockchip_saradc_data *data;
197
198 data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
199 priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
200 if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
201 pr_err("Dev: %s - can't get address!", dev->name);
202 return -ENODATA;
203 }
204
205 priv->data = data;
206 uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;
207 uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
208 uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
209 uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
210
211 return 0;
212 }
213
214 static const struct adc_ops rockchip_saradc_ops = {
215 .start_channel = rockchip_saradc_start_channel,
216 .channel_data = rockchip_saradc_channel_data,
217 .stop = rockchip_saradc_stop,
218 };
219
220 static const struct rockchip_saradc_data rk3588_saradc_data = {
221 .num_bits = 12,
222 .num_channels = 8,
223 .clk_rate = 1000000,
224 };
225
226 static const struct rockchip_saradc_data rk3562_saradc_data = {
227 .num_bits = 10,
228 .num_channels = 8,
229 .clk_rate = 1000000,
230 };
231
232 static const struct rockchip_saradc_data rk1106_saradc_data = {
233 .num_bits = 10,
234 .num_channels = 2,
235 .clk_rate = 1000000,
236 };
237
238 static const struct udevice_id rockchip_saradc_ids[] = {
239 {
240 .compatible = "rockchip,rk3588-saradc",
241 .data = (ulong)&rk3588_saradc_data
242 },
243 {
244 .compatible = "rockchip,rk3528-saradc",
245 .data = (ulong)&rk3588_saradc_data
246 },
247 {
248 .compatible = "rockchip,rk3562-saradc",
249 .data = (ulong)&rk3562_saradc_data
250 },
251 {
252 .compatible = "rockchip,rv1106-saradc",
253 .data = (ulong)&rk1106_saradc_data
254 },
255 { }
256 };
257
258 U_BOOT_DRIVER(rockchip_saradc_v2) = {
259 .name = "rockchip_saradc_v2",
260 .id = UCLASS_ADC,
261 .of_match = rockchip_saradc_ids,
262 .ops = &rockchip_saradc_ops,
263 .probe = rockchip_saradc_probe,
264 .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,
265 .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv),
266 };
267