1*4882a593SmuzhiyunDisplay Controller 2*4882a593Smuzhiyun------------------ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun(there isn't yet a generic binding in Linux, so this describes what is in 5*4882a593SmuzhiyunU-Boot, and may change based on Linux activity) 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe device node for a display device is as described in the document 8*4882a593Smuzhiyun"Open Firmware Recommended Practice : Universal Serial Bus" with the 9*4882a593Smuzhiyunfollowing modifications and additions : 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties : 12*4882a593Smuzhiyun - compatible : Should be "nvidia,tegra20-dc" 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired subnode 'rgb' is as follows: 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties (rgb) : 17*4882a593Smuzhiyun - nvidia,panel : phandle of LCD panel information 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe panel node describes the panel itself. This has the properties listed in 21*4882a593Smuzhiyundisplaymode.txt as well as: 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunRequired properties (panel) : 24*4882a593Smuzhiyun - nvidia,bits-per-pixel: number of bits per pixel (depth) 25*4882a593Smuzhiyun - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt) 26*4882a593Smuzhiyun - nvidia,panel-timings: 4 cells containing required timings in ms: 27*4882a593Smuzhiyun * delay before asserting panel_vdd 28*4882a593Smuzhiyun * delay between panel_vdd-rise and data-rise 29*4882a593Smuzhiyun * delay between data-rise and backlight_vdd-rise 30*4882a593Smuzhiyun * delay between backlight_vdd and pwm-rise 31*4882a593Smuzhiyun * delay between pwm-rise and backlight_en-rise 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional GPIO properies all have (phandle, GPIO number, flags): 34*4882a593Smuzhiyun - nvidia,backlight-enable-gpios: backlight enable GPIO 35*4882a593Smuzhiyun - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO 36*4882a593Smuzhiyun - nvidia,backlight-vdd-gpios: backlight power GPIO 37*4882a593Smuzhiyun - nvidia,panel-vdd-gpios: panel power GPIO 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunhost1x { 42*4882a593Smuzhiyun compatible = "nvidia,tegra20-host1x", "simple-bus"; 43*4882a593Smuzhiyun reg = <0x50000000 0x00024000>; 44*4882a593Smuzhiyun interrupts = <0 65 0x04 /* mpcore syncpt */ 45*4882a593Smuzhiyun 0 67 0x04>; /* mpcore general */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ranges = <0x54000000 0x54000000 0x04000000>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun dc@54200000 { 54*4882a593Smuzhiyun compatible = "nvidia,tegra20-dc"; 55*4882a593Smuzhiyun reg = <0x54200000 0x00040000>; 56*4882a593Smuzhiyun interrupts = <0 73 0x04>; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun rgb { 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun nvidia,panel = <&lcd_panel>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunlcd_panel: panel { 67*4882a593Smuzhiyun /* Seaboard has 1366x768 */ 68*4882a593Smuzhiyun clock = <70600000>; 69*4882a593Smuzhiyun xres = <1366>; 70*4882a593Smuzhiyun yres = <768>; 71*4882a593Smuzhiyun left-margin = <58>; 72*4882a593Smuzhiyun right-margin = <58>; 73*4882a593Smuzhiyun hsync-len = <58>; 74*4882a593Smuzhiyun lower-margin = <4>; 75*4882a593Smuzhiyun upper-margin = <4>; 76*4882a593Smuzhiyun vsync-len = <4>; 77*4882a593Smuzhiyun hsync-active-high; 78*4882a593Smuzhiyun nvidia,bits-per-pixel = <16>; 79*4882a593Smuzhiyun nvidia,pwm = <&pwm 2 0>; 80*4882a593Smuzhiyun nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */ 81*4882a593Smuzhiyun nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ 82*4882a593Smuzhiyun nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ 83*4882a593Smuzhiyun nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ 84*4882a593Smuzhiyun nvidia,panel-timings = <400 4 203 17 15>; 85*4882a593Smuzhiyun}; 86