xref: /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/video/rockchip-lvds.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunRockchip LVDS interface
2*4882a593Smuzhiyun------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunRequired properties:
5*4882a593Smuzhiyun- compatible: "rockchip,rk3288-lvds";
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun- reg: physical base address of the controller and length
8*4882a593Smuzhiyun	of memory mapped region.
9*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the
10*4882a593Smuzhiyun	clock-names property.
11*4882a593Smuzhiyun- clock-names: must contain "pclk_lvds"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun- rockchip,grf: phandle to the general register files syscon
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or  <LVDS_FORMAT_JEIDA>,
16*4882a593Smuzhiyun	This describes how the color bits are laid out in the
17*4882a593Smuzhiyun	serialized LVDS signal.
18*4882a593Smuzhiyun- rockchip,data-width : should be <18> or <24>;
19*4882a593Smuzhiyun- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
20*4882a593Smuzhiyun	<LVDS_OUTPUT_DUAL>, This describes the output face.
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun- display-timings : described by
23*4882a593Smuzhiyun	doc/devicetree/device-tree-bindings/video/display-timing.txt.
24*4882a593Smuzhiyun
25*4882a593SmuzhiyunExample:
26*4882a593Smuzhiyun	lvds: lvds@ff96c000 {
27*4882a593Smuzhiyun		compatible = "rockchip,rk3288-lvds";
28*4882a593Smuzhiyun		reg = <0xff96c000 0x4000>;
29*4882a593Smuzhiyun		clocks = <&cru PCLK_LVDS_PHY>;
30*4882a593Smuzhiyun		clock-names = "pclk_lvds";
31*4882a593Smuzhiyun		pinctrl-names = "default";
32*4882a593Smuzhiyun		pinctrl-0 = <&lcdc0_ctl>;
33*4882a593Smuzhiyun		rockchip,grf = <&grf>;
34*4882a593Smuzhiyun		status = "disabled";
35*4882a593Smuzhiyun		ports {
36*4882a593Smuzhiyun			#address-cells = <1>;
37*4882a593Smuzhiyun			#size-cells = <0>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun			lvds_in: port@0 {
40*4882a593Smuzhiyun				reg = <0>;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun				#address-cells = <1>;
43*4882a593Smuzhiyun				#size-cells = <0>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun				lvds_in_vopb: endpoint@0 {
46*4882a593Smuzhiyun					reg = <0>;
47*4882a593Smuzhiyun					remote-endpoint = <&vopb_out_lvds>;
48*4882a593Smuzhiyun				};
49*4882a593Smuzhiyun				lvds_in_vopl: endpoint@1 {
50*4882a593Smuzhiyun					reg = <1>;
51*4882a593Smuzhiyun					remote-endpoint = <&vopl_out_lvds>;
52*4882a593Smuzhiyun				};
53*4882a593Smuzhiyun			};
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	&lvds {
58*4882a593Smuzhiyun		rockchip,data-mapping = <LVDS_FORMAT_VESA>;
59*4882a593Smuzhiyun		rockchip,data-width = <24>;
60*4882a593Smuzhiyun		rockchip,output = <LVDS_OUTPUT_DUAL>;
61*4882a593Smuzhiyun		rockchip,panel = <&panel>;
62*4882a593Smuzhiyun		status = "okay";
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		display-timings {
65*4882a593Smuzhiyun			timing@0 {
66*4882a593Smuzhiyun				clock-frequency = <40000000>;
67*4882a593Smuzhiyun				hactive = <1920>;
68*4882a593Smuzhiyun				vactive = <1080>;
69*4882a593Smuzhiyun				hsync-len = <44>;
70*4882a593Smuzhiyun				hfront-porch = <88>;
71*4882a593Smuzhiyun				hback-porch = <148>;
72*4882a593Smuzhiyun				vfront-porch = <4>;
73*4882a593Smuzhiyun				vback-porch = <36>;
74*4882a593Smuzhiyun				vsync-len = <5>;
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun	};
78