1*4882a593SmuzhiyunAtmel HLCDC Framebuffer 2*4882a593Smuzhiyun----------------------------------------------------- 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : 5*4882a593Smuzhiyun "atmel,sama5d2-hlcdc", "atmel,at91sam9x5-hlcdc". 6*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 7*4882a593Smuzhiyun region. 8*4882a593Smuzhiyun- clocks: phandles to input clocks. 9*4882a593Smuzhiyun- atmel,vl-bpix: Bits per pixel. 10*4882a593Smuzhiyun- atmel,output-mode: LCD Controller Output Mode, 11*4882a593Smuzhiyun The unit is bits per pixel, there are four values, 12*4882a593Smuzhiyun <12>, <16>, <18>, <24>, the default value is <24>. 13*4882a593Smuzhiyun- atmel,guard-time: lcd guard time (Delay in frame periods). 14*4882a593Smuzhiyun- display-timings: please refer the displaymode.txt. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyunhlcdc: hlcdc@f0000000 { 18*4882a593Smuzhiyun u-boot,dm-pre-reloc; 19*4882a593Smuzhiyun compatible = "atmel,sama5d2-hlcdc"; 20*4882a593Smuzhiyun reg = <0xf0000000 0x2000>; 21*4882a593Smuzhiyun clocks = <&lcdc_clk>; 22*4882a593Smuzhiyun atmel,vl-bpix = <4>; 23*4882a593Smuzhiyun atmel,output-mode = <24>; 24*4882a593Smuzhiyun atmel,guard-time = <1>; 25*4882a593Smuzhiyun pinctrl-names = "default"; 26*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun display-timings { 30*4882a593Smuzhiyun 480x272 { 31*4882a593Smuzhiyun clock-frequency = <9000000>; 32*4882a593Smuzhiyun hactive = <480>; 33*4882a593Smuzhiyun vactive = <272>; 34*4882a593Smuzhiyun hsync-len = <41>; 35*4882a593Smuzhiyun hfront-porch = <2>; 36*4882a593Smuzhiyun hback-porch = <2>; 37*4882a593Smuzhiyun vfront-porch = <2>; 38*4882a593Smuzhiyun vback-porch = <2>; 39*4882a593Smuzhiyun vsync-len = <11>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43