1*4882a593SmuzhiyunQualcomm SPMI arbiter/bus driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is bus driver for Qualcomm chips that use SPMI to communicate with PMICs. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: "qcom,spmi-pmic-arb" 7*4882a593Smuzhiyun- reg: Register block adresses and sizes for various parts of device: 8*4882a593Smuzhiyun 1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn) 9*4882a593Smuzhiyun 2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS) 10*4882a593Smuzhiyun 3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS) 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties (if not set by parent): 13*4882a593Smuzhiyun- #address-cells: 0x1 - childs slave ID address 14*4882a593Smuzhiyun- #size-cells: 0x1 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunAll PMICs should be placed as a child nodes of bus arbiter. 17*4882a593SmuzhiyunAutomatic detection of childs is currently not supported. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunspmi@200f000 { 22*4882a593Smuzhiyun compatible = "qcom,spmi-pmic-arb"; 23*4882a593Smuzhiyun reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>; 24*4882a593Smuzhiyun #address-cells = <0x1>; 25*4882a593Smuzhiyun #size-cells = <0x1>; 26*4882a593Smuzhiyun}; 27