1*4882a593SmuzhiyunCadence SPI controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6". 6*4882a593Smuzhiyun- reg : Physical base address and size of SPI registers map. 7*4882a593Smuzhiyun- interrupts : Property with a value describing the interrupt 8*4882a593Smuzhiyun number. 9*4882a593Smuzhiyun- interrupt-parent : Must be core interrupt controller 10*4882a593Smuzhiyun- clock-names : List of input clock names - "ref_clk", "pclk" 11*4882a593Smuzhiyun (See clock bindings for details). 12*4882a593Smuzhiyun- clocks : Clock phandles (see clock bindings for details). 13*4882a593Smuzhiyun- spi-max-frequency : Maximum SPI clocking speed of device in Hz 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- num-cs : Number of chip selects used. 17*4882a593Smuzhiyun If a decoder is used, this will be the number of 18*4882a593Smuzhiyun chip selects after the decoder. 19*4882a593Smuzhiyun- is-decoded-cs : Flag to indicate whether decoder is used or not. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun spi@e0007000 { 24*4882a593Smuzhiyun compatible = "xlnx,zynq-spi-r1p6"; 25*4882a593Smuzhiyun clock-names = "ref_clk", "pclk"; 26*4882a593Smuzhiyun clocks = <&clkc 26>, <&clkc 35>; 27*4882a593Smuzhiyun interrupt-parent = <&intc>; 28*4882a593Smuzhiyun interrupts = <0 49 4>; 29*4882a593Smuzhiyun num-cs = <4>; 30*4882a593Smuzhiyun is-decoded-cs = <0>; 31*4882a593Smuzhiyun reg = <0xe0007000 0x1000>; 32*4882a593Smuzhiyun } ; 33