1*4882a593SmuzhiyunCadence QSPI controller device tree bindings 2*4882a593Smuzhiyun-------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : should be "cadence,qspi". 6*4882a593Smuzhiyun- reg : 1.Physical base address and size of SPI registers map. 7*4882a593Smuzhiyun 2. Physical base address & size of NOR Flash. 8*4882a593Smuzhiyun- clocks : Clock phandles (see clock bindings for details). 9*4882a593Smuzhiyun- sram-size : spi controller sram size. 10*4882a593Smuzhiyun- status : enable in requried dts. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunconnected flash properties 13*4882a593Smuzhiyun-------------------------- 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- spi-max-frequency : Max supported spi frequency. 16*4882a593Smuzhiyun- page-size : Flash page size. 17*4882a593Smuzhiyun- block-size : Flash memory block size. 18*4882a593Smuzhiyun- tshsl-ns : Added delay in master reference clocks (ref_clk) for 19*4882a593Smuzhiyun the length that the master mode chip select outputs 20*4882a593Smuzhiyun are de-asserted between transactions. 21*4882a593Smuzhiyun- tsd2d-ns : Delay in master reference clocks (ref_clk) between one 22*4882a593Smuzhiyun chip select being de-activated and the activation of 23*4882a593Smuzhiyun another. 24*4882a593Smuzhiyun- tchsh-ns : Delay in master reference clocks between last bit of 25*4882a593Smuzhiyun current transaction and de-asserting the device chip 26*4882a593Smuzhiyun select (n_ss_out). 27*4882a593Smuzhiyun- tslch-ns : Delay in master reference clocks between setting 28*4882a593Smuzhiyun n_ss_out low and first bit transfer 29