1*4882a593SmuzhiyunSoft SPI 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe soft SPI bus implementation allows the use of GPIO pins to simulate a 4*4882a593SmuzhiyunSPI bus. No SPI host is required for this to work. The down-side is that the 5*4882a593Smuzhiyunperformance will typically be much lower than a real SPI bus. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe soft SPI node requires the following properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyuncompatible: "u-boot,soft-spi" 10*4882a593Smuzhiyunsoft_spi_cs: GPIO number to use for SPI chip select (output) 11*4882a593Smuzhiyunsoft_spi_sclk: GPIO number to use for SPI clock (output) 12*4882a593Smuzhiyunsoft_spi_mosi: GPIO number to use for SPI MOSI line (output) 13*4882a593Smuzhiyunsoft_spi_miso GPIO number to use for SPI MISO line (input) 14*4882a593Smuzhiyunspi-delay-us: Number of microseconds of delay between each CS transition 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe GPIOs should be specified as required by the GPIO controller referenced. 17*4882a593SmuzhiyunThe first cell holds the phandle of the controller and the second cell 18*4882a593Smuzhiyuntypically holds the GPIO number. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun soft-spi { 24*4882a593Smuzhiyun compatible = "u-boot,soft-spi"; 25*4882a593Smuzhiyun cs-gpio = <&gpio 235 0>; /* Y43 */ 26*4882a593Smuzhiyun sclk-gpio = <&gpio 225 0>; /* Y31 */ 27*4882a593Smuzhiyun mosi-gpio = <&gpio 227 0>; /* Y33 */ 28*4882a593Smuzhiyun miso-gpio = <&gpio 224 0>; /* Y30 */ 29*4882a593Smuzhiyun spi-delay-us = <1>; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <0>; 32*4882a593Smuzhiyun cs@0 { 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35