1*4882a593Smuzhiyun* Synopsys DesignWare ABP UART 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "snps,dw-apb-uart" 5*4882a593Smuzhiyun- reg : offset and length of the register set for the device. 6*4882a593Smuzhiyun- interrupts : should contain uart interrupt. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunClock handling: 9*4882a593SmuzhiyunThe clock rate of the input clock needs to be supplied by one of 10*4882a593Smuzhiyun- clock-frequency : the input clock frequency for the UART. 11*4882a593Smuzhiyun- clocks : phandle to the input clock 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe supplying peripheral clock can also be handled, needing a second property 14*4882a593Smuzhiyun- clock-names: tuple listing input clock names. 15*4882a593Smuzhiyun Required elements: "baudclk", "apb_pclk" 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE 19*4882a593Smuzhiyun configuration parameter. Define this if your UART does not implement the busy 20*4882a593Smuzhiyun functionality. 21*4882a593Smuzhiyun- resets : phandle to the parent reset controller. 22*4882a593Smuzhiyun- reg-shift : quantity to shift the register offsets by. If this property is 23*4882a593Smuzhiyun not present then the register offsets are not shifted. 24*4882a593Smuzhiyun- reg-io-width : the size (in bytes) of the IO accesses that should be 25*4882a593Smuzhiyun performed on the device. If this property is not present then single byte 26*4882a593Smuzhiyun accesses are used. 27*4882a593Smuzhiyun- dcd-override : Override the DCD modem status signal. This signal will always 28*4882a593Smuzhiyun be reported as active instead of being obtained from the modem status 29*4882a593Smuzhiyun register. Define this if your serial port does not use this pin. 30*4882a593Smuzhiyun- dsr-override : Override the DTS modem status signal. This signal will always 31*4882a593Smuzhiyun be reported as active instead of being obtained from the modem status 32*4882a593Smuzhiyun register. Define this if your serial port does not use this pin. 33*4882a593Smuzhiyun- cts-override : Override the CTS modem status signal. This signal will always 34*4882a593Smuzhiyun be reported as active instead of being obtained from the modem status 35*4882a593Smuzhiyun register. Define this if your serial port does not use this pin. 36*4882a593Smuzhiyun- ri-override : Override the RI modem status signal. This signal will always be 37*4882a593Smuzhiyun reported as inactive instead of being obtained from the modem status register. 38*4882a593Smuzhiyun Define this if your serial port does not use this pin. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun uart@80230000 { 43*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 44*4882a593Smuzhiyun reg = <0x80230000 0x100>; 45*4882a593Smuzhiyun clock-frequency = <3686400>; 46*4882a593Smuzhiyun interrupts = <10>; 47*4882a593Smuzhiyun reg-shift = <2>; 48*4882a593Smuzhiyun reg-io-width = <4>; 49*4882a593Smuzhiyun dcd-override; 50*4882a593Smuzhiyun dsr-override; 51*4882a593Smuzhiyun cts-override; 52*4882a593Smuzhiyun ri-override; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample with one clock: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun uart@80230000 { 58*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 59*4882a593Smuzhiyun reg = <0x80230000 0x100>; 60*4882a593Smuzhiyun clocks = <&baudclk>; 61*4882a593Smuzhiyun interrupts = <10>; 62*4882a593Smuzhiyun reg-shift = <2>; 63*4882a593Smuzhiyun reg-io-width = <4>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunExample with two clocks: 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun uart@80230000 { 69*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 70*4882a593Smuzhiyun reg = <0x80230000 0x100>; 71*4882a593Smuzhiyun clocks = <&baudclk>, <&apb_pclk>; 72*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 73*4882a593Smuzhiyun interrupts = <10>; 74*4882a593Smuzhiyun reg-shift = <2>; 75*4882a593Smuzhiyun reg-io-width = <4>; 76*4882a593Smuzhiyun }; 77